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| 19-4384; Rev 1; 7/09 Microcontroller with 10-Bit ADC, PGA, 64KB Flash, and CAN Interface General Description The MAXQ7670 is a highly integrated solution for measuring multiple analog signals and outputting the results on a control area network (CAN) bus. The device operates from a single 5V supply and incorporates a highperformance, 16-bit reduced instruction set computing (RISC) core, a SAR ADC, and a CAN 2.0B controller, supporting transfer rates up to 1Mbps. The 10-bit SAR ADC includes an amplifier with programmable gains of 1V/V or 16V/V, 8 input channels, and conversion rates up to 250ksps. The eight single-ended ADC inputs can be configured as four unipolar or bipolar, fully differential inputs. For single-supply operation, the external 5V supply powers the digital I/Os and two separate integrated linear regulators that supply the 2.5V digital core and the 3.3V analog circuitry. Each supply rail has a dedicated power-supply supervisor that provides brownout detection and power-on reset (POR) functions. The 16-bit RISC microcontroller (C) includes 64KB (32K x 16) of nonvolatile program/data flash and 2KB (1K x 16) of data RAM. Other features of the MAXQ7670 include a 4-wire SPITM interface, a JTAG interface for in-system programming and debugging, an integrated 15MHz RC oscillator, external crystal oscillator support, a timer/counter with pulse-width modulation (PWM) capability, and seven GPIO pins with interrupt and wake-up capability. The system-on-a-chip (SoC) MAXQ7670 is a C-based, smart data acquisition system. As a member of the MAXQ(R) family of 16-bit, RISC Cs, the MAXQ7670 is ideal for low-cost, low-power, embedded-applications such as automotive, industrial controls, and building automation. The flexible, modular architecture used in the MAXQ Cs allows development of targeted products for specific applications with minimal effort. The MAXQ7670 is available in a 40-pin, 5mm x 5mm TQFN package, and is specified to operate over the -40C to +125C automotive temperature range. Features o High-Performance, Low-Power, 16-Bit RISC Core 0.166MHz to 16MHz Operation, Approaching 1MIPs/MHz Low Power (< 1mA/MIPS, VDVDD = +2.5V) 16-Bit Instruction Word, 16-Bit Data Bus 33 Instructions, Most Require Only One Clock Cycle 16-Level Hardware Stack 16 x 16-Bit, General-Purpose Working Registers Three Independent Data Pointers with AutoIncrement/Decrement Low-Power, Divide-by-256, Power-Management Modes (PMM) and Stop Mode o Program and Data Memory 64KB Internal Nonvolatile Program/Data Flash 2KB Internal Data RAM o SAR ADC 8 Single-Ended/4 Differential Channels, 10-Bit Resolution with No Missing Codes PGA Gain = 1V/V or 16V/V 250ksps (150.9ksps with PGA Gain = 16V/V) o Timer/Digital I/O Peripherals CAN 2.0B Controller (15 Message Centers) Serial Peripheral Interface (SPI) JTAG Interface (Extensive Debug and Emulation Support) Single 16-Bit/Dual 8-Bit Timer/PWM Seven General-Purpose, Digital I/O Pins with External Interrupt/Wake-Up Features o Oscillator/Clock Module Internal Oscillator Supports External Crystal (8MHz or 16MHz) Integrated 15MHz RC Oscillator External Clock Source Operation Programmable Watchdog Timer o Power-Management Module Power-On Reset Power-Supply Supervisor/Brownout Detection Integrated +2.5V and +3.3V Linear Regulators MAXQ7670 Applications Automotive Steering Angle and Torque Sensors CAN-Based Automotive Sensor Applications Industrial Control Building Automation SPI is a trademark of Motorola, Inc. MAXQ is a registered trademark of Maxim Integrated Products, Inc. PART MAXQ7670ATL/V+ Ordering Information TEMP RANGE -40C to +125C PIN-PACKAGE 40 TQFN-EP* /V denotes an automotive qualified part. +Denotes a lead-free/RoHS-compliant package. *EP = Exposed pad. Typical Application Circuit and Pin Configuration appear at end of data sheet. Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device may be simultaneously available through various sales channels. For information about device errata, go to: http://www.maxim-ic.com/errata. ________________________________________________________________ Maxim Integrated Products 1 For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com. Microcontroller with 10-Bit ADC, PGA, 64KB Flash, and CAN Interface MAXQ7670 ABSOLUTE MAXIMUM RATINGS DVDD to DGND ........................................................-0.3V to +3V DVDDIO to GNDIO ................................................-0.3V to +5.5V AVDD to AGND ........................................................-0.3V to +4V DGND to GNDIO. ..................................................-0.3V to +0.3V GNDIO to AGND. ..................................................-0.3V to +0.3V AGND to DGND.....................................................-0.3V to +0.3V Analog Inputs to AGND..........................-0.3V to (VAVDD + 0.3V) RESET, Digital Inputs/Outputs to GNDIO ............................................-0.3V to (VDVDDIO + 0.3V) XIN, XOUT to DGND ..............................-0.3V to (VDVDD + 0.3V) Continuous Power Dissipation (TA = +70C) 40-Pin TQFN (derate 36mW/C above +70C) ..........2857mW Continuous Current into Any Pin.......................................50mA Operating Temperature Range .........................-40C to +125C Junction Temperature ......................................................+150C Storage Temperature Range .............................-65C to +150C Lead Temperature (soldering, 10s) ................................+300C Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (VDVDDIO = +5.0V, VAVDD = +3.3V, VDVDD = +2.5V, VREFADC = +3.3V, system clock = 16MHz. TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.) (Note 1) PARAMETER POWER REQUIREMENTS DVDD Supply Voltage Ranges AVDD DVDDIO AVDD Supply Current IAVDD Shutdown (Note 2) All analog functions enabled ADC, 50ksps, 4MHz ADCCLK Analog Module Incremental Subfunction Supply Current IAVDD ADC, 250ksps, 4MHz ADCCLK AVDD brownout interrupt monitor PGA enabled CPU in stop mode, all peripherals disabled DVDD Supply Current IDVDD High speed/2MHz mode (Note 3) High speed/16MHz mode (Note 4) Low speed/625kHz mode (Note 5) Program flash erase or write DVDDIO brownout reset monitor Digital Peripheral Incremental Subfunction Supply Current IDVDD HF crystal oscillator Internal fixed-frequency oscillator All digital I/Os static at GNDIO or DVDDIO CAN transmitting, timer output switching (Note 6) REGEN2 = DVDDIO, DVDD AVDD, DVDD DVDDIO LRAPD = 1, AVDD DVDDIO 2.25 3.0 4.5 2.5 3.3 5.0 3 6 5200 5600 3 5500 25 2.0 11.3 0.95 14 1 60 50 2 0.2 20 0.3 A mA A 23 200 2.5 mA A A 2.75 3.6 5.25 10 7 A mA V SYMBOL CONDITIONS MIN TYP MAX UNITS DVDDIO Supply Current IDVDDIO 2 _______________________________________________________________________________________ Microcontroller with 10-Bit ADC, PGA, 64KB Flash, and CAN Interface ELECTRICAL CHARACTERISTICS (continued) (VDVDDIO = +5.0V, VAVDD = +3.3V, VDVDD = +2.5V, VREFADC = +3.3V, system clock = 16MHz. TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.) (Note 1) PARAMETER MEMORY SECTION Flash Memory Size Flash Page Size Flash Erase/Write Endurance Flash Data Retention (Note 7) Flash Erase Time Flash Programming Time RAM Memory Size Utility ROM Size Resolution NADC 16-bit word size No missing codes PGA gain = 16V/V, bipolar mode, VIN = 100mV, 150.9ksps PGA gain = 1V/V, unipolar mode, VIN = +1.0V, 250ksps PGA gain = 1V/V or 16V/V Test at TA = +25C, PGA gain = 1V/V or 16V/V PGA gain = 16V/V, bipolar mode PGA gain = 16V/V, bipolar mode, excludes offset and reference error, test at TA = +25C PGA gain = 16V/V, bipolar mode fADCCLK fSAMPLE fSYSCLK = 8MHz or 16MHz PGA gain = 16V/V, fADCCLK = 4MHz PGA gain = 1V/V, fADCCLK = 4MHz PGA gain = 16V/V, 13.5 ADCCLK cycles at 4MHz tACQ PGA gain = 1V/V, three ADCCLK cycles at 4MHz 13 ADCCLK cycles at 4MHz 3.375 s 0.75 3.25 s 0.5 10 0.5 0.4 0.4 1 2 1 LSB10 1 1 10 LSB10 mV V/C ANALOG SENSE PATH (Includes PGA and ADC) Bits Program or data storage 16-bit word size Program or data (Note 7) All flash, TA = +25C All flash, TA = +85C Flash page erase Entire flash mass erase Flash single word programming Entire flash programming 10,000 100 15 20 200 20 0.66 2 4 50 500 40 1.31 64 256 KB Words Cycles Years ms s s KB KWords SYMBOL CONDITIONS MIN TYP MAX UNITS MAXQ7670 Integral Nonlinearity INLADC Differential Nonlinearity Input-Referred Offset Error Offset-Error Temperature Coefficient Gain Error Gain-Error Temperature Coefficient Conversion Clock Frequency Sample Rate DNLADC -2 +2 % 5 4.0 150.9 250 ppm/C MHz ksps Channel Select, Track-andHold Acquisition Time Conversion Time tCONV _______________________________________________________________________________________ 3 Microcontroller with 10-Bit ADC, PGA, 64KB Flash, and CAN Interface MAXQ7670 ELECTRICAL CHARACTERISTICS (continued) (VDVDDIO = +5.0V, VAVDD = +3.3V, VDVDD = +2.5V, VREFADC = +3.3V, system clock = 16MHz. TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.) (Note 1) PARAMETER Channel Select Plus Conversion Time Turn-On Time Aperture Delay Aperture Jitter At AIN0-AIN7, unipolar mode, PGA gain = 1V/V At AIN0-AIN7, unipolar mode, PGA gain = 16V/V At AIN0-AIN7, bipolar mode, PGA gain = 1V/V At AIN0-AIN7, bipolar mode, PGA gain = 16V/V Absolute Input Voltage Range Input Leakage Current Input-Referred Noise Small-Signal Bandwidth (-3dB) Large-Signal Bandwidth (-3dB) At AIN0-AIN7 At AIN0-AIN7 At AIN0-AIN7, PGA gain = 16V/V At AIN0-AIN7, PGA gain = 1V/V VIN = 12mVP-P, PGA gain = 16V/V VIN = 200mVP-P, PGA gain = 1V/V VIN = 150mVP-P, PGA gain =16V/V VIN = 2.5VP-P, PGA gain = 1V/V Single-ended, any AIN0-AIN7, PGA gain = 16V/V Input Capacitance (Note 8) Single-ended, any AIN0-AIN7, PGA gain = 1V/V Input Common-Mode Rejection Ratio Power-Supply Rejection Ratio EXTERNAL REFERENCE INPUTS REFADC Input Voltage Range REFADC Leakage Current Input Capacitance +3.3V (AVDD) LINEAR REGULATOR AVDD Output Voltage No-Load Quiescent Current LRAPD = 0 LRAPD = 0, all internal analog peripherals disabled 3.15 3.3 10 3.45 V A ADC disabled (Note 9) 1.0 3.3 1 20 VAVDD V A pF CMRR PSRR AIN0-AIN7, VCM = differential input range AVDD = 3.0V to 3.6V 13 75 90 dB dB 0 0 -VREFADC /2 -VREFADC /32 0 0.1 50 400 33 23 33 19 16 pF SYMBOL tACQ + tCONV tRECOV CONDITIONS PGA gain = 16V/V, 26.5 ADCCLK cycles at 4MHz PGA gain = 1V/V, 16 ADCCLK cycles at 4MHz MIN TYP 6.625 s 4 10 60 100 VREFADC 0.125 V +VREFADC /2 +VREFADC /32 VAVDD V A VRMS MHz MHz s ns psP-P MAX UNITS Differential Input Voltage Range 4 _______________________________________________________________________________________ Microcontroller with 10-Bit ADC, PGA, 64KB Flash, and CAN Interface ELECTRICAL CHARACTERISTICS (continued) (VDVDDIO = +5.0V, VAVDD = +3.3V, VDVDD = +2.5V, VREFADC = +3.3V, system clock = 16MHz. TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.) (Note 1) PARAMETER Output Current Capability Output Short-Circuit Current Maximum AVDD Bypass Capacitor to AGND +2.5V (DVDD) LINEAR REGULATOR DVDD Output Voltage No-Load Quiescent Current Output Current Capability Output Short-Circuit Current Maximum DVDD Bypass Capacitor to DGND REGEN2 = GNDIO REGEN2 = GNDIO, all internal digital peripherals disabled REGEN2 = GNDIO REGEN2 = GNDIO, DVDD shorted to DGND REGEN2 = GNDIO 50 100 0.47 2.38 2.5 15 2.62 V A mA mA F SYMBOL LRAPD = 0 LRAPD = 0, AVDD shorted to AGND LRAPD = 0 CONDITIONS MIN 50 100 0.47 TYP MAX UNITS mA mA F MAXQ7670 SUPPLY-VOLTAGE SUPERVISORS AND BROWNOUT DETECTION DVDD Reset Threshold DVDD Interrupt Threshold Minimum DVDD Interrupt and Reset Threshold Difference AVDD Interrupt Threshold DVDDIO Interrupt Threshold Generates an interrupt if VAVDD falls below this threshold Generates an interrupt if VDVDDIO falls below this threshold DVDD Operational Range Supervisor Hysteresis CAN INTERFACE CAN Baud Rate CANCLK Mean Frequency Error CANCLK Total Frequency Error fCANCLK = 8MHz 8MHz or 16MHz, 50ppm external crystal 8MHz or 16MHz, 50ppm external crystal; measured over a 12ms interval; mean plus peak cycle jitter 60 1 Mbps ppm AVDD DVDDIO 3.0 4.5 1 1 1 0.7 Asserts RESET if VDVDD is below this threshold Generates an interrupt if VDVDD falls below this threshold 2.1 2.25 0.14 3.15 4.75 2.75 3.6 5.25 % V 2.25 2.38 V V V V V < 0.5 % _______________________________________________________________________________________ 5 Microcontroller with 10-Bit ADC, PGA, 64KB Flash, and CAN Interface MAXQ7670 ELECTRICAL CHARACTERISTICS (continued) (VDVDDIO = +5.0V, VAVDD = +3.3V, VDVDD = +2.5V, VREFADC = +3.3V, system clock = 16MHz. TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.) (Note 1) PARAMETER SYMBOL CONDITIONS Using external crystal External input (Note 10) Excluding crystal drift fSYSCLK cycles Driven with external clock source Driven with external clock source 0.7 x VDVDD 13.8 15 0.4 5 1.5 16.35 0.166 25 65,535 0.3 x VDVDD MIN TYP 8 or 16 MAX 16 16.67 UNITS HIGH-FREQUENCY CRYSTAL OSCILLATOR Clock Frequency Stability Startup Time XIN Input Low Voltage XIN Input High Voltage MHz ppm Cycles V V INTERNAL FIXED-FREQUENCY OSCILLATOR Frequency Tolerance Temperature Drift Power-Supply Rejection RESET (RESET) RESET Internal Pullup Resistance RESET Output Low Voltage RESET Output High Voltage RESET Input Low Voltage RESET Input High Voltage Pulled up to DVDDIO RESET asserted, no external load RESET deasserted, no external load Driven with external clock source Driven with external clock source 0.7 x VDVDDIO 0.8 2.1 500 VIN = GNDIO or VDVDDIO, pullup disabled -10 0.01 55 55 15 ISINK = 0.5mA ISOURCE = 0.5mA VDVDDIO - 0.5 0.4 +10 0.9 x VDVDDIO 0.3 x VDVDD 55 0.4 k V V V V fIFFCLK TA = TMIN to TMAX TA = +25C TA = TMIN to TMAX TA = +25C, DVDD = 2.25V to 2.75V MHz % % % DIGITAL INPUTS (P0._, CANRXD, MISO, MOSI, SS, SCLK, TCK, TDI, TMS) Input Low Voltage Input High Voltage Input Hysteresis Input Leakage Current Input Pullup Resistance Input Pulldown Resistance Input Capacitance DIGITAL OUTPUTS (P0._, CANTXD, MOSI, SCLK, SS, TDO) Output Low Voltage Output High Voltage V V V V mV A k k pF 6 _______________________________________________________________________________________ Microcontroller with 10-Bit ADC, PGA, 64KB Flash, and CAN Interface ELECTRICAL CHARACTERISTICS (continued) (VDVDDIO = +5.0V, VAVDD = +3.3V, VDVDD = +2.5V, VREFADC = +3.3V, system clock = 16MHz. TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.) (Note 1) PARAMETER Output Capacitance Maximum Output Impedance SYSTEM CLOCK System Clock Frequency SPI INTERFACE TIMING SPI Master Operating Frequency SPI Slave Mode Operating Frequency SCLK Output Pulse-Width High/Low SCLK Input Pulse-Width High/Low MOSI Output Hold Time After SCLK Sample Edge MOSI Output Setup Time to SCLK Sample Edge MISO Input Setup Time to SCLK Sample Edge MISO Input Hold Time After SCLK Sample Edge SCLK Inactive to MOSI Inactive MOSI Input Setup Time to SCLK Sample Edge MOSI Input Hold Time After SCLK Sample Edge MISO Output Valid After SCLK Shift Edge Transition MISO Output Disabled After SS Edge Rise SS Falling Edge to MISO Active fMCLK fSCLK tMCH, tMCL tSCH, tSCL tMOH tMOS tMIS tMIH tMLH tSIS tSIH tSOV tSLH tSOE 2 tSYSCLK + 2.5 tSYSCLK - 25 tSYSCLK - 25 30 0 tSYSCLK - 25 30 tSYSCLK + 25 3 tSYSCLK + 25 2 tSYSCLK + 50 tSYSCLK - 25 tSYSCLK 0.5 x fSYSCLK 8 fSYSCLK/8 MHz MHz ns ns ns ns ns ns ns ns ns ns ns ns fSYSCLK From any clock source 0 16.67 MHz SYMBOL PD0._ = 0 PD0._ = 1 CONDITIONS I/O pins three-state MIN TYP 15 880 450 MAX UNITS pF MAXQ7670 _______________________________________________________________________________________ 7 Microcontroller with 10-Bit ADC, PGA, 64KB Flash, and CAN Interface MAXQ7670 ELECTRICAL CHARACTERISTICS (continued) (VDVDDIO = +5.0V, VAVDD = +3.3V, VDVDD = +2.5V, VREFADC = +3.3V, system clock = 16MHz. TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.) (Note 1) PARAMETER SS Falling Edge to First SCLK Sample Edge SCLK Inactive to SS Rising Edge Minimum CS Pulse Width SYMBOL tSSE tSD tSCW CONDITIONS MIN 2 tSYSCLK +5 tSYSCLK + 10 tSYSCLK + 10 TYP MAX UNITS ns ns ns Note 1: All devices are 100% production tested at TA = +25C and +125C. Temperature limits to TA = -40C are guaranteed by design. Note 2: All analog functions disabled and all digital inputs connected to supply or ground. Note 3: High-speed/8 mode without CAN; VDVDD = +2.5V, CPU and 16-bit timer running at 2MHz from an external, 16MHz crystal oscillator; all other peripherals disabled; all digital I/Os static at VDVDDIO or GNDIO; TA = TMIN to TMAX. Note 4: High-speed/1 mode with CAN; VDVDD = +2.5V, CPU and 16-bit timer running at 16MHz from an external, 16MHz crystal oscillator; CAN enabled and communicating at 500kbps; all other peripherals disabled, all digital I/Os (except CANTXD and CANRXD) static at VDVDDIO or GNDIO, TA = TMIN to TMAX. Note 5: Low speed, PMM1 mode without CAN; VDVDD = +2.5V, CPU and one timer running from an external, 16MHz crystal oscillator in PMM1 mode; all other peripherals disabled; all digital I/Os static at VDVDDIO or GNDIO, TA = TMIN to TMAX. Note 6: CAN transmitting at 500kbps; 16-bit timer output switching at 500kHz; all active I/Os are loaded with a 20pF capacitor; all remaining digital I/Os are static at VDVDDIO or GNDIO, TA = TMIN to TMAX. Note 7: Guaranteed by design and characterization. Note 8: This is not a static capacitance. It is the capacitance presented to the analog input when the T/H amplifier is in sample mode. Note 9: The switched capacitor on the REFADC input can disturb the reference voltage. To reduce this disturbance, place a 0.1F capacitor from REFADC to AGND as close as possible to REFADC. Note 10: The digital design is fully static. However, the lower clock limit is set by a clock detect circuit. The MAXQ7670 switches to the internal RC clock if the external input goes below 166kHz. This clock detect circuit also acts to detect a crystal failure when a crystal is used. 8 _______________________________________________________________________________________ Microcontroller with 10-Bit ADC, PGA, 64KB Flash, and CAN Interface MAXQ7670 SAMPLE EDGE SHIFT EDGE tMCLK tMCL SCLK (CKPOL/CKPHA = 0/1 OR 1/0 MODE) tMCH SCLK (CKPOL/CKPHA = 0/0 OR 1/1 MODE) tMIS MISO tMIH tMCH tMCL tMOS MOSI tMOH tMLH HIGH IMPEDANCE Figure 1. SPI Timing Diagram in Master Mode tSCW SAMPLE EDGE SHIFT EDGE tSCLK tSD SS tSSE SCLK (CKPOL/CKPHA = 0/1 OR 1/0 MODE) tSCL tSCH tSCH SCLK (CKPOL/CKPHA = 0/0 OR 1/1 MODE) tSIS MOSI tSIH tSCL tSOE MISO HIGH IMPEDANCE tSOV tSLH HIGH IMPEDANCE Figure 2. SPI Timing Diagram in Slave Mode _______________________________________________________________________________________ 9 Microcontroller with 10-Bit ADC, PGA, 64KB Flash, and CAN Interface MAXQ7670 Typical Operating Characteristics (VDVDDIO = 5.0V, VAVDD = 3.3V, VDVDD = 2.5V, fSYSCLK = 16MHz, ADC resolution = 10 bits, VREFDAC = 3.3V, TA = +25C, unless otherwise noted.) GPO._ OUTPUT HIGH VOLTAGE vs. SOURCE CURRENT PS0._ = 1 PS0._ = 0 TA = -40C VOH (V) 3 TA = +25C 2 TA = +85C 1 TA = +105C 0 0 0.5 1.0 1.5 IOH (mA) 2.0 2.5 TA = +105C 0 0 0.5 1.0 1.5 IOL (mA) 2.0 2.5 TA = +85C 1 TA = +25C TA = -40C VOL (V) 3 PS0._ = 0 TA = -40C 2 TA = +25C TA = +85C TA = +105C -1.0 -1.5 -512 -256 0 256 DIGITAL OUTPUT CODE 512 MAXQ7670 toc01 GPO._ OUTPUT LOW VOLTAGE vs. SINK CURRENT MAXQ7670 toc02 ADC INL vs. CODE (REF ADC = +3.3V, 150.9ksps, PGA GAIN = 16V/V) BIPOLAR MODE VIN = -100mV TO +100mV MAXQ7670 toc03 MAXQ7670 toc09 MAXQ7670 toc06 5 5 PS0._ = 1 4 TA = +105C TA = +85C TA = +25C TA = -40C 1.5 1.0 0.5 0 -0.5 4 ADC DNL vs. CODE (REFADC = +3.3V, 150.9ksps, PGA GAIN = 16V/V) MAXQ7670 toc04 ADC INL (LSB) ADC OFFSET ERROR vs. TEMPERATURE MAXQ7670 toc05 ADC GAIN ERROR vs. TEMPERATURE 1.0 0.8 0.6 GAIN ERROR (%) 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 BIPOLAR MODE PGA GAIN = 16V/V VIN-DIFF = 200mV VIN-CM = +1.65V 1.0 0.8 0.6 0.4 ADC DNL (LSB) 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 -512 -256 0 256 DIGITAL OUTPUT CODE BIPOLAR MODE VIN = -100mV to +100mV 2.0 1.8 1.6 OFFSET ERROR (mV) 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 BIPOLAR MODE PGA GAIN = 16V/V VIN-DIFF = 0 VIN-CM = +1.65V 512 -40 -25 -10 5 20 35 50 65 80 95 110 125 TEMPERATURE (C) -40 -25 -10 5 20 35 50 65 80 95 110 125 TEMPERATURE (C) DVDD, RESET POWER-UP CHARACTERISTICS MAXQ7670 toc07 DVDD, RESET POWER-DOWN CHARACTERISTICS MAXQ7670 toc08 MAXIMUM DVDD TRANSIENT DURATION vs. BOI THRESHOLD OVERDRIVE 200 DVDDIO 2V/div MAXIMUM TRANSIENT DURATION (s) 180 160 140 120 100 80 60 40 20 0 1 10 100 1000 DVDD BOI THRESHOLD OVERDRIVE (mV) BOI ASSERTED ABOVE THIS LINE DVDDIO 2V/div DVDD 1V/div DVDD 1V/div REGEN2 = GNDIO RESET 2V/div REGEN2 = GNDIO RESET 2V/div 10ms/div 20ms/div 10 ______________________________________________________________________________________ Microcontroller with 10-Bit ADC, PGA, 64KB Flash, and CAN Interface Typical Operating Characteristics (continued) (VDVDDIO = 5.0V, VAVDD = 3.3V, VDVDD = 2.5V, fSYSCLK = 16MHz, ADC resolution = 10 bits, VREFDAC = 3.3V, TA = +25C, unless otherwise noted.) MAXIMUM DVDDIO TRANSIENT DURATION vs. BOI THRESHOLD OVERDRIVE MAXQ7670 toc10 MAXQ7670 MAXIMUM AVDD TRANSIENT DURATION vs. BOI THRESHOLD OVERDRIVE MAXQ7670 toc11 AVDD LINEAR REGULATOR OUTPUT VOLTAGE vs. DVDDIO SUPPLY VOLTAGE 3.5 3.0 AVDD (V) 2.5 2.0 1.5 1.0 0.5 0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 DVDDIO (V) LRAPD = 0 IOUT = 10mA MAXQ7670 toc12 200 MAXIMUM TRANSIENT DURATION (s) 180 160 140 120 100 80 60 40 20 0 1 BOI ASSERTED ABOVE THIS LINE 200 MAXIMUM TRANSIENT DURATION (s) 180 160 140 120 100 80 60 40 20 0 1 BOI ASSERTED ABOVE THIS LINE 4.0 10 100 1000 DVDDIO BOI THRESHOLD OVERDRIVE (mV) 10 100 1000 AVDD BOI THRESHOLD OVERDRIVE (mV) AVDD LINEAR REGULATOR OUTPUT VOLTAGE vs. TEMPERATURE MAXQ7670 toc13 AVDD LINEAR REGULATOR OUTPUT VOLTAGE vs. LOAD CURRENT MAXQ7670 toc14 DVDD LINEAR REGULATOR OUTPUT VOLTAGE vs. DVDDIO SUPPLY VOLTAGE REGEN2 = DVDDIO IOUT = 10mA MAXQ7670 toc15 3.40 LRAPD = 0 IOUT = 10mA 3.35 AVDD (V) 3.40 LRAPD = 0 3.35 3.0 2.5 2.0 3.30 3.30 DVDD (V) 0 5 10 15 20 25 30 35 40 45 50 LOAD CURRENT (mA) AVDD (V) 1.5 1.0 3.25 3.25 0.5 3.20 -40 -25 -10 5 20 35 50 65 80 95 110 125 TEMPERATURE (C) 3.20 0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 DVDDIO (V) DVDD LINEAR REGULATOR OUTPUT VOLTAGE vs. TEMPERATURE MAXQ7670 toc16 DVDD LINEAR REGULATOR OUTPUT VOLTAGE vs. LOAD CURRENT MAXQ7670 toc17 RC OSCILLATOR OUTPUT FREQUENCY vs. TEMPERATURE MAXQ7670 toc18 2.60 REGEN2 = DVDDIO IOUT = 10mA 2.55 DVDD (V) 2.60 REGEN2 = DVDDIO 2.55 17.0 16.5 FREQUENCY (MHz) 16.0 15.5 15.0 14.5 DVDD (V) 2.50 2.50 2.45 2.45 2.40 -40 -25 -10 5 20 35 50 65 80 95 110 125 TEMPERATURE (C) 2.40 0 5 10 15 20 25 30 35 40 45 50 LOAD CURRENT (mA) 14.0 -40 -25 -10 5 20 35 50 65 80 95 110 125 TEMPERATURE (C) ______________________________________________________________________________________ 11 Microcontroller with 10-Bit ADC, PGA, 64KB Flash, and CAN Interface MAXQ7670 Typical Operating Characteristics (continued) (VDVDDIO = 5.0V, VAVDD = 3.3V, VDVDD = 2.5V, fSYSCLK = 16MHz, ADC resolution = 10 bits, VREFDAC = 3.3V, TA = +25C, unless otherwise noted.) RC OSCILLATOR OUTPUT FREQUENCY vs. DVDD MAXQ7670 toc19 DVDD SUPPLY CURRENT vs. DVDD SUPPLY VOLTAGE MAXQ7670 toc020 DVDD SUPPLY CURRENT vs. TEMPERATURE 18 DVDD SUPPLY CURRENT (mA) 16 14 12 10 8 6 4 2 0 NOTE 3 IN EC CHARACTERISTICS NOTE 5 IN EC CHARACTERISTICS NOTE 4 IN EC CHARACTERISTICS FLASH ERASE MAXQ7670 toc21 16.0 20 18 DVDD SUPPLY CURRENT (mA) 16 14 12 10 8 6 4 2 NOTE 3 IN EC CHARACTERISTICS NOTE 5 IN EC CHARACTERISTICS NOTE 4 IN EC CHARACTERISTICS FLASH ERASE 20 15.5 FREQUENCY (MHz) 15.0 14.5 14.0 2.25 2.35 2.45 2.55 DVDD (V) 2.65 2.75 0 2.250 2.375 2.500 2.625 2.750 -40 -25 -10 5 20 35 50 65 80 95 110 125 TEMPERATURE (C) DVDD SUPPLY VOLTAGE (V) DVDD SUPPLY CURRENT vs. DVDD SUPPLY VOLTAGE MAXQ7670 toc22 DVDD SUPPLY CURRENT vs. TEMPERATURE MAXQ7670 toc23 AVDD SUPPLY CURRENT vs. AVDD SUPPLY VOLTAGE SHUTDOWN (NOTE 2) IN EC CHARACTERISTICS MAXQ7670 toc24 26.5 STOP MODE DVDD SUPPLY CURRENT (A) 26.0 25.5 25.0 24.5 24.0 23.5 2.250 28 27 26 25 24 23 22 STOP MODE 140 120 AVDD SUPPLY CURRENT (nA) 100 80 60 40 20 0 DVDD SUPPLY CURRENT (A) 2.375 2.500 2.625 2.750 -40 -25 -10 5 20 35 50 65 80 95 110 125 TEMPERATURE (C) 3.00 3.15 3.30 3.45 3.60 DVDD SUPPLY VOLTAGE (V) AVDD SUPPLY VOLTAGE (V) AVDD SUPPLY CURRENT vs. TEMPERATURE MAXQ7670 toc25 AVDD SUPPLY CURRENT vs. AVDD SUPPLY VOLTAGE ALL ANALOG FUNCTIONS ENABLED AVDD SUPPLY CURRENT (mA) MAXQ7670 toc26 AVDD SUPPLY CURRENT vs. TEMPERATURE ALL ANALOG FUNCTIONS ENABLED AVDD SUPPLY CURRENT (mA) 6.0 MAXQ7670 toc27 140 120 AVDD SUPPLY CURRENT (nA) 100 80 60 40 20 0 SHUTDOWN (NOTE 2) IN EC CHARACTERISTICS 6.0 6.2 5.9 5.8 5.8 5.6 5.7 5.4 5.6 -40 -25 -10 5 20 35 50 65 80 95 110 125 TEMPERATURE (C) 3.00 3.15 3.30 3.45 3.60 AVDD SUPPLY VOLTAGE (V) 5.2 -40 -25 -10 5 20 35 50 65 80 95 110 125 TEMPERATURE (C) 12 ______________________________________________________________________________________ Microcontroller with 10-Bit ADC, PGA, 64KB Flash, and CAN Interface Typical Operating Characteristics (continued) (VDVDDIO = 5.0V, VAVDD = 3.3V, VDVDD = 2.5V, fSYSCLK = 16MHz, ADC resolution = 10 bits, VREFDAC = 3.3V, TA = +25C, unless otherwise noted.) AVDD SUPPLY CURRENT vs. ADC SAMPLING RATE MAXQ7670 toc28 MAXQ7670 DVDDIO DYNAMIC SUPPLY CURRENT vs. DVDDIO SUPPLY VOLTAGE MAXQ7670 toc29 DVDDIO DYNAMIC SUPPLY CURRENT vs. TEMPERATURE NOTE 6 IN EC CHARACTERISTICS DVDDIO SUPPLY CURRENT (A) 240 MAXQ7670 toc30 5.7 PGA GAIN = 16V/V AVDD SUPPLY CURRENT (mA) 260 NOTE 6 IN EC CHARACTERISTICS 240 DVDDIO SUPPLY CURRENT (A) 220 200 180 160 140 120 250 5.6 230 220 5.5 210 5.4 1 10 100 1000 ADC SAMPLING RATE (ksps) 100 2.250 200 2.375 2.500 2.625 2.750 -40 -25 -10 5 20 35 50 65 80 95 110 125 TEMPERATURE (C) DVDDIO SUPPLY VOLTAGE (V) DVDDIO STATIC SUPPLY CURRENT vs. DVDDIO SUPPLY VOLTAGE MAXQ7670 toc31 DVDDIO STATIC SUPPLY CURRENT vs. TEMPERATURE MAXQ7670 toc32 DVDDIO INCREMENTAL SUPPLY CURRENT vs. DVDDIO SUPPLY VOLTAGE BOI ENABLED DVDDIO SUPPLY CURRENT (A) 4 MAXQ7670 toc33 160 DVDDIO SUPPLY CURRENT (A) 140 120 100 80 60 40 4.750 160 DVDDIO SUPPLY CURRENT (A) 140 120 100 80 60 40 5 3 2 1 4.875 5.00 5.125 5.250 -40 -25 -10 5 20 35 50 65 80 95 110 125 TEMPERATURE (C) 0 4.750 4.875 5.000 5.125 5.250 DVDDIO SUPPLY VOLTAGE (V) DVDDIO SUPPLY VOLTAGE (V) DVDDIO INCREMENTAL SUPPLY CURRENT vs. TEMPERATURE BOI ENABLED DVDDIO SUPPLY CURRENT (A) 4 MAXQ7670 toc34 ADC SAMPLING ERROR vs. INPUT SOURCE IMPEDANCE MAXQ7670 toc35 SNR fIN = 10kHz fS = 62.5ksps MAXQ7670 toc36 5 1 0 SAMPLING ERROR (LSB) -1 -2 -3 -4 -5 0 -20 -40 MAGNITUDE (dB) -60 -80 -100 3 2 1 0 -40 -25 -10 5 20 35 50 65 80 95 110 125 TEMPERATURE (C) PGA GAIN = 16V/V fS = 150.9ksps 1 10 100 1000 10,000 100,000 SOURCE IMPEDANCE () -120 -140 0 5 10 15 20 25 FREQUENCY (kHz) 30 35 ______________________________________________________________________________________ 13 Microcontroller with 10-Bit ADC, PGA, 64KB Flash, and CAN Interface MAXQ7670 Pin Description PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15, 22, 38 16 17 NAME AIN7 AIN6 AIN5 AIN4 REFADC AGND AIN3 AIN2 AIN1 AIN0 I.C. P0.0 P0.1 P0.2 GNDIO CANRXD CANTXD FUNCTION Analog Input Channel 7. AIN7 is multiplexed to the PGA or ADC as single-ended analog input 7 or as a differential input with AIN6. As a differential input, the polarity of AIN7 is negative. Analog Input Channel 6. AIN6 is multiplexed to the PGA or ADC as a single-ended analog input 6 or as a differential input with AIN7. As a differential input, the polarity of AIN6 is positive. Analog Input Channel 5. AIN5 is multiplexed to the PGA or ADC as single-ended analog input 5 or as a differential input with AIN4. As a differential input, the polarity of AIN5 is negative. Analog Input Channel 4. AIN4 is multiplexed to the PGA or ADC as single-ended analog input 4 or as a differential input with AIN5. As a differential input, the polarity of AIN4 is positive. ADC External Reference Input. Connect an external reference between 1V and VAVDD. Analog Ground Analog Input Channel 3. AIN3 is multiplexed to the PGA or ADC as single-ended analog input 3 or as a differential input with AIN2. As a differential input, the polarity of AIN3 is negative. Analog Input Channel 2. AIN2 is multiplexed to the PGA or ADC as single-ended analog input 2 or as a differential input with AIN3. As a differential input, the polarity of AIN2 is positive. Analog Input Channel 1. AIN1 is multiplexed to the PGA or ADC as single-ended analog input 1 or as a differential input with AIN0. As a differential input, the polarity of AIN1 is negative. Analog Input Channel 0. AIN0 is multiplexed to the PGA or ADC as single-ended analog input 0 or as a differential input with AIN1. As a differential input, the polarity of AIN0 is positive. Internally Connected. Connect to GNDIO for proper operation. Port 0 Bit 0. P0.0 is a general-purpose digital I/O with interrupt/wake-up capability. Port 0 Bit 1. P0.1 is a general-purpose digital I/O with interrupt/wake-up capability. Port 0 Bit 2. P0.2 is a general-purpose digital I/O with interrupt/wake-up capability. Digital I/O Ground and Regulator Ground CAN Bus Receiver Input. CAN receiver input. CAN Bus Transmitter Output. CAN transmitter output. Active-Low, SPI Port Slave Select Input. In SPI slave mode, this is the slave select input. In SPI master mode, this is an input and connection is optional (connect if mode fault enable is required, refer to the MAXQ7670 User's Guide for a description of the SPICN register). In master mode, use an available GPIO as a slave selector and pull SS high to DVDDIO through a pullup resistor. Port 0 Bit 6/Timer 0 I/O. P0.6 is a general-purpose digital I/O with interrupt/wake-up input capability. T0 is a primary timer/PWM input or output. The alternative function, T0, is selected using the T2CNA0 register. When this function is selected, it overrides the GPIO functionality. Port 0 Bit 7/Timer 0 Output. P0.7 is a general-purpose digital I/O with interrupt/wake-up input capability. T0B is a secondary timer/PWM output. The alternative function, T0B, is selected using the T2CNB0 register. When this function is selected, it overrides the GPIO functionality. Digital I/O Supply Voltage and Regulator Supply Input. DVDDIO supplies all digital I/O except for XIN and XOUT, and supplies power to the two internal linear regulators, AVDD and DVDD. Bypass DVDDIO to GNDIO with a 0.1F capacitor as close as possible to the device. 18 SS 19 P0.6/T0 20 P0.7/T0B 21, 39 DVDDIO 14 ______________________________________________________________________________________ Microcontroller with 10-Bit ADC, PGA, 64KB Flash, and CAN Interface Pin Description (continued) PIN 23 24 25 26 27 28 29 30 NAME SCLK MOSI MISO REGEN2 TDO TMS TDI TCK FUNCTION SPI Serial Clock. SCLK is the SPI interface serial clock I/O. In SPI master mode, SCLK is an output. While in SPI slave mode, SCLK is an input. SPI Serial Data I/O. MOSI is the SPI interface serial data output in master mode or serial data input in slave mode. SPI Serial Data I/O. MISO is the SPI interface serial data input in master mode or serial data output in slave mode. Active-Low +2.5V Linear Regulator Enable Input. Connect REGEN2 to GNDIO to enable the +2.5V linear regulator. Connect to DVDDIO to disable the +2.5V linear regulator. JTAG Serial Test Data Output. TDO is the JTAG serial test, data output. JTAG Test Mode Select. TMS is the JTAG test mode, select input. JTAG Serial Test Data Input. TDI is the JTAG serial test, data input. JTAG Serial Test Clock Input. TCK is the JTAG serial test, clock input. Port 0 Bit 4/ADC Start Conversion Control. P0.4 is a general-purpose digital I/O with interrupt/wake-up capability. ADCCNV is a firmware-configurable, rising or falling edge, start/convert signal used to trigger ADC conversions. The alternative function, ADCCNV, is selected using the register bits ACNT[2:0]. When using ADCCNV as a trigger for ADC conversion, set P0.4/ADCCNV as an input using the PD0 register. This action prevents any unintentional interference in the SARADC operation. Port 0 Bit 5. P0.5 is a general-purpose digital I/O with interrupt/wake-up capability. Reset Input/Output. Active-low input/output with internal 55k pullup to DVDDIO. Drive low to reset the MAXQ7670. The MAXQ20 C core holds RESET low during POR and during DVDD brownout conditions. Digital Ground High-Frequency Crystal Output. Connect an external crystal to XIN and XOUT for normal operation, or leave unconnected if XIN is driven with an external clock source. Leave unconnected if an external clock source is not used. High-Frequency Crystal Input. Connect an external crystal or resonator to XIN and XOUT for normal operation, or drive XIN with an external clock source. Leave unconnected if an external clock source is not used. Digital Supply Voltage. DVDD supplies internal digital core and flash memory. DVDD is directly connected to the output of the internal +2.5V linear regulator. Disable the internal regulator (through REGEN2) to connect an external supply. Bypass DVDD to DGND with a 0.1F capacitor as close as possible to the device. Analog Supply Voltage. AVDD supplies PGA and ADC. AVDD is directly connected to the output of the internal +3.3V linear regulator. Disable the internal regulator (via software) to connect an external supply. Bypass AVDD to AGND with a 0.1F capacitor as close as possible to the device. Exposed Pad. Connect EP to the ground plane. MAXQ7670 31 P0.4/ ADCCNV P0.5 RESET DGND XOUT 32 33 34 35 36 XIN 37 DVDD 40 -- AVDD EP ______________________________________________________________________________________ 15 Microcontroller with 10-Bit ADC, PGA, 64KB Flash, and CAN Interface MAXQ7670 Block Diagram DVDDIO AIN0 AIN1 AIN2 AIN3 AIN4 AIN5 AIN6 AIN7 10:1 MUX ADCREF ADCCLK PGAE PGA 10-BIT ADC LRAPD DVDDIO ADCCNV ADCBY REFADC GAIN = 1x, 16x ADCRY ADCE DVDDIO +3.3V LINEAR REGAULATOR AVDD AVDD AIN1 AIN3 AIN5 AIN7 AIN9 AGND GNDIO 6:1 MUX ADCMX[3:0] HFFINT EIFO SPI SOFTWAREINTERRUPT CONTROLLER CANSTI CANERI VIOBI VIBE DVDDIO BROWNOUT MONITOR DVDDIO GNDIO T0I VABI VABE AVDD BROWNOUT MONITOR AGND MAXQ7670 DVDDIO +2.5V LINEAR REGAULATOR IFFCLK DVDDIO EWT WTR GNDIO RESET DVDD DGND DVDD POWER-ON RESET MONITOR DVDD 4K x 16 UTILITY ROM 16-BIT MAXQ20 CORE RISC CPU WATCHDOG TIMER WDI DVDD T0CLK T0I 16-BIT TIMER0 P0.7/T0B P0.6/T0 P0.5 P0.4/ADCCNV P0.2 P0.1 P0.0 REGEN2 64KB (32K x 16) PROGRAM/DATA FLASH 2KB (1K x 16) DATA RAM PD0 PO0 PI0 EIF0 PORT 0 I/O REGISTERS I/O BUFFERS VDPE DVDDIO DGND TCK TDI TMS TDO I/O BUFFERS JTAG INTERFACE PORT 0 I/O REGISTERS SS SCLK DVDD GNDIO CAN CLOCK PRESCALER ADC CLOCK PRESCALER M U X HFCLK HF CLOCK PRESCALER CANCLK DGND SPI SERIAL PERIPHERAL INTERFACE (SPI) MOSI MISO GNDIO DVDDIO XIN XOUT HF XTAL OSC. HFFINT XHFRY HFE ADCCLK DGND GNDIO DGND GNDIO IFE DGND INT FIXED FREQ OSC. IFFCLK SYSCLK TIMER CLOCK PRESCALER 2:1 M U X SYSCLK CANSTI CANERI CAN 2.0B INTERFACE I/O BUFFERS CANTXD CANRXD T0CLK CANCLK GNDIO 16 ______________________________________________________________________________________ Microcontroller with 10-Bit ADC, PGA, 64KB Flash, and CAN Interface Detailed Description The MAXQ7670 incorporates a 16-bit RISC arithmetic logic unit (ALU) with a Harvard memory architecture that addresses 64KB (32K x 16) of flash and 2048 bytes (1024 x 16) of RAM memory. This core combined with digital and analog peripherals provide versatile data-acquisition functions. The peripherals include up to seven digital I/Os, a 4-wire SPI interface, a CAN 2.0B bus, a JTAG interface, a timer, an integrated RC oscillator, two linear regulators, a watchdog timer, three power-supply supervisors, a 10-bit 250ksps SAR ADC with programmable-gain amplifier (PGA) and eight single-ended or four differential multiplexed inputs. The power-efficient MAXQ20 C core consumes less than 1mA/MIPS. Refer to the MAXQ7670 User's Guide for more detailed information on configuring and programming the MAXQ7670. MAXQ7670 Analog Input Peripheral The integrated 10-bit ADC employs an ultra-low-power SAR-based conversion method and operates up to 250ksps with PGA = 1V/V (150.9ksps with PGA = 16V/V). The integrated 8-channel multiplexer (mux) and PGA allow the ADC to measure eight single-ended (relative to AGND) or four fully differential analog inputs with software-selectable input ranges through the PGA. See Figures 3 and 4. MAXQ7670 P0.4/ADCCNV TIMER 0 ADCBY ACTL 10 ADCDUL CONVERSION CONTROL AIN0 AIN1 AIN2 AIN3 AIN4 AIN5 AIN6 AIN7 AGND ADCE 3 ADCMX 210 ADC CLOCK DIV 2 PGG 8:1 MUX ADCBIP ADCRDY PGA 1V/V OR 16V/V 10-BIT ADC 250ksps 10 DATA BUS ADCASD ADCCLK SOURCE REFADC 10 ADCCD Figure 3. Simplified Analog Input Diagram (Eight Single-Ended Inputs) ______________________________________________________________________________________ 17 Microcontroller with 10-Bit ADC, PGA, 64KB Flash, and CAN Interface MAXQ7670 MAXQ7670 P0.4/ADCCNV TIMER 0 ADCBY ACTL 10 ADCDUL CONVERSION CONTROL 2 AIN0 AIN2 AIN4 AIN6 4:1 MUX PGG ADCBIP ADCRDY DATA BUS PGA 1V/V OR 16V/V AIN1 AIN3 AIN5 AIN7 4:1 MUX ADCE 10-BIT ADC 250ksps 10 ADCASD ADC CLOCK DIV ADCCLK SOURCE ADCMX 3210 REFADC 10 ADCCD Figure 4. Simplified Analog Input Diagram (Four Fully Differential Inputs) 18 ______________________________________________________________________________________ Microcontroller with 10-Bit ADC, PGA, 64KB Flash, and CAN Interface The MAXQ7670 ADC uses a fully differential SAR conversion technique and an integrated T/H (track and hold) block to convert voltage signals into a 10-bit digital result. Both single-ended and differential configurations are implemented using an analog input channel multiplexer that supports 8 single-ended or 4 differential channels. In single-ended mode, the mux selects from either of the ground-referenced analog inputs AIN0-AIN7. In differential input configuration, analog inputs are selected from the following pairs: AIN0/AIN1, AIN2/AIN3, AIN4/AIN5, and AIN6/AIN7. Table 1 shows the singleended and differential input configurations possible for the ADC mux. Gain = 1V/V In gain = 1V/V, the conversion has a two-stage T/H cycle. In track mode, a positive input capacitor connects to the signal channel. A negative input capacitor connects to the reference channel. After the T/H enters hold mode, the difference between the signal and the reference channel is converted to a 10-bit value. This two-stage cycle takes 16 SARCLKs to complete. MAXQ7670 Gain = 16V/V In gain = 16V/V, the conversion has a three-stage T/H cycle: amplification, ADC track, and ADC hold. First, the PGA tracks the selected input and reference signals. The PGA amplifies the difference between the two signals and holds the result for the next stage, ADC track. The ADC tracks and converts the PGA result into a 10-bit value. The SAR operation itself does not change irrespective of the chosen gain. This threestage cycle takes 26.5 SARCLKs to complete. Figure 5 shows the conversion timing differences between gain = 1V/V and gain = 16V/V. Analog Input Track and Hold A SAR conversion in the MAXQ7670 has different T/H cycles depending on whether a gain of 1 (bypass) or a gain of 16 (PGA enabled) is selected. Table 1. ADC Mux Input Configurations SAR CHANNEL SELECT (REGISTER ACNT[14:11]) 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 SIGNAL CHANNEL INTO ADC AIN0 AIN1 AIN2 AIN3 AIN4 AIN5 AIN6 AIN7 -- -- AIN0 AIN2 AIN4 AIN6 -- -- REFERENCE CHANNEL INTO ADC AGND AGND AGND AGND AGND AGND AGND AGND -- -- AIN1 AIN3 AIN5 AIN7 -- -- MEASUREMENT TYPE Single-ended measurement on AIN0 Single-ended measurement on AIN1 Single-ended measurement on AIN2 Single-ended measurement on AIN3 Single-ended measurement on AIN4 Single-ended measurement on AIN5 Single-ended measurement on AIN6 Single-ended measurement on AIN7 Reserved Reserved AIN0/AIN1 AIN2/AIN3 AIN4/AIN5 AIN6/AIN7 Reserved VCIM differential zero offset trim ______________________________________________________________________________________ 19 Microcontroller with 10-Bit ADC, PGA, 64KB Flash, and CAN Interface MAXQ7670 3 SCLK SAR CYCLE PGA = 1V/V 13 SCLK SAR TRACK HOLD AND SAR CONVERT 7.5 SCLK SAR CYCLE PGA = 16V/V 6 SCLK 13 SCLK PGA TRACK PGA HOLD, SAR TRACK HOLD AND SAR CONVERT Figure 5. Conversion Timing Differences Between Gain = 1V/V and Gain = 16V/V Input Impedance The input-capacitance charging rate determines the time required for the T/H to acquire an input signal. The required acquisition time lengthens with the increase of the input signals source resistance. Any source below 5k does not significantly affect the ADC's performance. A high-impedance source can be accommodated by placing a 1F capacitor between the input channel and AGND. The combination of analog-input source impedance and the capacitance at the analog input creates an RC filter that limits the analog-input bandwidth. Controlling ADC Conversions Use the following methods to control the ADC conversion timing: 1) Software register bit control 2) Continuous conversion 3) Internal timer (T0) 4) External input through ADCCNV Refer to the MAXQ7670 User's Guide for more detailed information on the ADC and mux. APE register. By continually checking for low supply voltages, appropriate action can be taken for brownout conditions. Startup Using Internal Regulators Once the +5V DVDDIO supply reaches approximately 1.25V, the +2.5V linear regulator turns on and DVDD begins ramping. Between the DVDD levels of 1V and the reset threshold, the DVDD monitor holds RESET low. DVDD releases RESET after reaching the reset threshold. The MAXQ7670 jumps to the reset vector location (8000h in the utility ROM). During this time, DVDD finishes ramping to its nominal voltage of +2.5V. During this POR time, the software-enabled +3.3V linear regulator remains off. Turn on the +3.3V linear regulator after the MAXQ7670 has completed its bootup routines and is running application code. To turn on the +3.3V regulator, set the LRAPD bit in the APE register to 0. The AVDD supply begins ramping to its nominal voltage of +3.3V. Brownout Detectors The MAXQ7670 features brownout monitors for the +5V DVDDIO, +3.3V AVDD, and +2.5V DVDD power supplies. When enabled, these monitors generate interrupts when DVDDIO, AVDD, or DVDD fall below their respective brownout thresholds. Monitoring the supply rails alerts the C to brownout conditions so appropriate action can be taken. Under normal conditions the DVDDIO brownout monitor signals a falling +5V supply before the DVDD or AVDD brownout monitors indicate that the +2.5V or +3.3V are falling. The exceptions to this condition are: * If either DVDD or AVDD are externally powered and the source of power is removed * If there is some type of device failure that pulls the regulator outputs low without affecting the +5V DVDDIO supply POR and Brownout The MAXQ7670 operates from a single, external +5V supply connected to the DVDDIO. DVDDIO is the supply rail for the digital I/O and the supply input for both integrated linear regulators. The +3.3V linear regulator powers AVDD, while the +2.5V linear regulator powers DVDD. Alternatively, connect REGEN2 to DVDDIO and apply external power supplies to AVDD and DVDD. Power supplies DVDDIO, DVDD, and AVDD each include a brownout monitor that alerts the C through an interrupt when the corresponding supply voltages drop below a defined threshold. This condition is generally referred to as brownout interrupt (BOI). Enable BOI by setting the VABE, VDBE, and VIBE bits in the 20 ______________________________________________________________________________________ Microcontroller with 10-Bit ADC, PGA, 64KB Flash, and CAN Interface The DVDD reset supervisor resets the MAXQ7670 when the +2.5V DVDD falls below the reset threshold. The processor remains in reset until DVDD returns above the reset threshold. The C does not execute commands in reset mode. See Figure 6 for the C response to DVDD brownout and reset. Refer to the MAXQ7670 User's Guide for detailed programming information, and a more thorough description of POR and brownout behavior. Internal 2.5V Linear Regulator The integrated 2.5V 50mA linear regulator or an external 2.5V supply applied at DVDD powers DVDD. Connect REGEN2 to GNDIO to enable the integrated regulator. Connect REGEN2 to DVDDIO to use an external supply. When using an external supply, connect a regulated 2.5V supply to DVDD after applying DVDDIO. MAXQ7670 DVDDIO Current Requirements Both internal linear regulators are capable of supplying up to 50mA each. When using the regulators to power AVDD and DVDD and to provide power to external devices, make sure DVDDIO's power input can source a current greater than the sum of the MAXQ7670 supply current and the load currents of the two regulators. Internal 3.3V Linear Regulator The integrated 3.3V 50mA linear regulator or an external 3.3V supply powers AVDD. The integrated 3.3V regulator is inactive upon power-up. Enable the integrated regulator with software programming after power-up. When using an external supply, connect a regulated 3.3V supply to AVDD after applying DVDDIO. NOMINAL DVDD (+2.5V) +2.38V +2.25V DVDD BROWNOUT INTERRUPT THRESHOLD RANGE BROWNOUT INTERRUPT (BOI) BROWNOUT RESET (BOR) INTERNAL RESET RESET OUTPUT BOR STATE DGND DVLVL FLAG (ASR[14]) VDBE BIT SET BY C DVBI FLAG (ASR[4]) FLAG ARBITRARILY CLEARED BY C Figure 6. DVDD Brownout and Reset Behavior ______________________________________________________________________________________ 21 Microcontroller with 10-Bit ADC, PGA, 64KB Flash, and CAN Interface MAXQ7670 System Clock Generator The MAXQ7670 oscillator module provides the master clock generator that supplies the system clock for the C core and all of the peripheral modules. The high-frequency oscillator operates with an 8MHz or 16MHz crystal. Alternatively, use the integrated RC oscillator in applications that do not require precise timing. The MAXQ7670 executes most instructions in a single SYSCLK period. The oscillator module contains all of the primary clock generation circuitry. Figure 7 shows a block diagram of the system clock module. The MAXQ7670 contains the following features for generating its master clock signal timing source: * Internal, fast-starting, 15MHz RC oscillator eliminates external crystal * Internal high-frequency oscillator that can drive an external 8MHz or 16MHz crystal * External high-frequency 0.166MHz to 16MHz clock input * Power-up timer * Power-saving management modes * Fail-safe modes 2) To detect an infinite loop in any of the tasks 3) To detect an arbitration deadlock involving two or more tasks 4) To detect if some lower priority tasks are not getting to run because of higher priority tasks As illustrated in Figure 8, the internal RC oscillator (CLK_RC) drives the watchdog timer through a series of dividers. The programmable divider output determines the timeout interval. When enabled, the interrupt flag WDIF sets. A system reset occurs after a time delay (based on the divider ratio) unless an interrupt service routine clears the watchdog interrupt. The watchdog timer functions as the source of both the watchdog interrupt and the watchdog reset. The interrupt timeout has a default divide ratio of 2 12 of the CLK_RC, with the watchdog reset set to timeout 2 9 clock cycles later. With the nominal RC oscillator value of 15MHz, an interrupt timeout occurs every 0.273ms, followed by a watchdog reset 34s later. The watchdog timer resets to the default divide ratio following any reset event. Use the WD0 and WD1 bits in the WDCN register to increase the watchdog interrupt period. Changing the WD[1:0] bits before a watchdog interrupt timeout occurs (i.e. before the watchdog reset counter begins) resets the watchdog timer count. The watchdog reset timeout occurs 512 RC oscillator cycles after the watchdog interrupt timeout. For more information on the MAXQ7670 watchdog timer, refer to the MAXQ7670 User's Guide. Watchdog Timer The primary function of the watchdog timer is to supervise software execution, watching for stalled or stuck software. The watchdog timer performs a controlled system restart when the C fails to write to the watchdog timer register before a selectable timeout interval expires. A watchdog timer typically has four objectives: 1) To detect if a system is operating normally CLK_RC (15MHz) HFE XIN XOUT RCE XT DIV 212 DIV 23 DIV 23 DIV 23 HF XTAL OSC EXTHF RC OSC CLK_RC MUX CLOCK DIVIDE SYSCLK WD1 WD0 RWT 212 215 218 221 TIME TIMEOUT WDIF INTERRUPT EWDI RESET EWT WTRF RESET CD1 CD0 PMME Figure 7. High-Frequency and RC Oscillator Functional Diagram Figure 8. Watchdog Functional Diagram 22 ______________________________________________________________________________________ Microcontroller with 10-Bit ADC, PGA, 64KB Flash, and CAN Interface Timer and PWM The MAXQ7670 includes a 16-bit timer channel. The timer offers two ports, T0 and T0B, to facilitate PWM outputs, and capture timing events. The autoreload 16bit timer/counter offers the following functions: * 8-/16-bit timer/counter * * * * * Up/down autoreload Counter function of external pulse Capture Compare PWM output Configure each of the first 14 message centers either to transmit or receive. Message center 15 is a receiveonly center, storing any message that centers 1-14 do not accept. A message center only accepts an incoming message if the following conditions are satisfied: * The incoming message's arbitration value matches the message center's acceptance identifier * The first 2 data bytes of the incoming message match the bytes in the media arbitration registers (C0MA0 and C0MA1) Use the global mask registers to mask out bits in the incoming message that do not require a comparison. A message center, configured to transmit, meets these conditions: T/R = 1, TIH = 0, DTUP = 1, MSRDY = 1, and MTRQ = 1. The message center transmits its contents when it receives an incoming request message containing the same identifier (i.e., a remote frame). Global control and status registers in the CAN unit enable the C to evaluate error messages, validate and locate new data, establish the bus timing for the CAN bus, establish the identification mask bits, and verify the source of individual messages. In addition, each message center is individually equipped with the necessary status and controls to establish directions, interrupt generation, identification mode (standard or extended), data field size, data status, automatic remote frame request and acknowledgment, and masked or nonmasked identification acceptance testing. The joint test action group (JTAG) IEEE(R) 1149.1 standard defines a unique method for in-circuit testing and programming. The MAXQ7670 conforms to this standard, implementing an external test access port (TAP) and internal TAP controller for communication with a JTAG bus master, such as an automatic test equipment (ATE). For detailed information on the TAP and TAP controller, refer to IEEE Standard 1149.1 on the IEEE website at www.standards.ieee.org. The JTAG on the MAXQ7670 does not support boundary scan test capability. MAXQ7670 * Event timer * System supervisor Refer to the MAXQ7670 User's Guide and Application Note 3205: Using Timers in the MAXQ Family of Microcontrollers for more information about the timer module. CAN Interface Bus The MAXQ7670 incorporates a fully compliant CAN 2.0B controller. Two groups of registers provide the C interface to the CAN controller. To simplify the software associated with the operation of the CAN controllers, most of the global CAN status and controls as well as the individual message center control/status registers are located in the peripheral register map. The remaining registers associated with the data identification, identification masks, format, and data are located in a dual port memory to allow the CAN controller and the processor access to the required functions. The CAN controller can directly access the dual port memory. The processor accesses the dual port memory through a dedicated interface that consists of the CAN 0 data pointer (C0DP) and the CAN 0 data buffer (C0DB) special function registers. See Figure 9 for CAN controller details. JTAG Interface Bus CAN Functional Description The CAN module stores up to 15 messages. Each message consists of an acceptance identifier and 8 bytes of data. The MAXQ7670 supports both the standard 11bit and extended 29-bit identification modes. IEEE is a registered service mark of the Institute of Electrical and Electronics Engineers. ______________________________________________________________________________________ 23 Microcontroller with 10-Bit ADC, PGA, 64KB Flash, and CAN Interface MAXQ7670 CAN 0 CONTROLLER BLOCK DIAGRAM DUAL PORT MEMORY MESSAGE CENTERS 1-15 MESSAGE CENTER 1 ARBITRATION 0-3 DATA 0-7 FORMAT 8-BIT Tx MESSAGE CENTER 2 ARBITRATION 0-3 DATA 0-7 FORMAT CAN PROTOCOL FSM CRC GENERATE BIT STUFF Tx SHIFT CANTXD 8-BIT Rx CRC CHECK CAN PROCESSOR BUS ACTIVITY WAKE-UP BIT DESTUFF Rx SHIFT BIT TIMING CANRXD CAN INTERRUPT SOURCES MESSAGE CENTER 14 ARBITRATION 0-3 DATA 0-7 FORMAT CAN 0 PERIPHERAL REGISTERS MESSAGE CENTER 15 ARBITRATION 0-3 DATA 0-7 FORMAT CAN 0 TRANSMIT ERROR COUNTER CAN 0 RECEIVE ERROR COUNTER CAN 0 CONTROL REGISTER CAN 0 OPERATION CONTROL CONTROL/STATUS/MASK REGISTERS MEDIA ID MASK 0-1 MEDIA ARBITRATION 0-1 BUS TIMING 0-1 STD GLOBAL MASK 0-1 EXT GLOBAL MASK 0-3 MSG15 MASK 0-3 CAN 0 MESSAGE 1-15 CONTROL REGISTERS CAN 0 DATA POINTER CAN 0 DATA BUFFER CAN 0 STATUS REGISTER CAN 0 INTERRUPT REGISTER CAN 0 TRANSMIT MSG ACK CAN 0 RECEIVE MSG ACK MAXQ7670 Figure 9. CAN 0 Controller Block Diagram The TAP controller communicates synchronously with the host system (bus master) through four digital I/Os: test mode select (TMS), test clock (TCK), test data input (TDI), and test data output (TDO). The internal TAP module consists of several shift registers and a TAP controller (see Figure 11). The shift registers serve as transmit-and-receive data buffers for a debugger. 4-Wire SPI Bus The MAXQ7670 includes a powerful hardware SPI module, providing serial communication with a wide variety of external devices. The SPI port on the MAXQ7670 is a fully independent module that is accessed through software. This full 4-wire, full-duplex serial bus module supports master and slave modes. The SPI clock 24 ______________________________________________________________________________________ Microcontroller with 10-Bit ADC, PGA, 64KB Flash, and CAN Interface frequency is limited to SYSCLK/2 in master mode and SYSCLK/8 in slave mode. Figure 10 shows the functional diagram of the SPI port. Figures 1 and 2 illustrate the timing parameters listed in the Electrical Characteristics table. each GPIO is configured as an input with a pullup to DVDDIO. In addition, each GPIO can be programmed to cause an interrupt (on falling or rising edges). In stop mode, use any interrupt to wake-up the device. The port direction (PD) register determines the input/output direction of each I/O. The port output (PO) register contains the current state of the logic output buffers. When an I/O is configured as an output, writing to the PO register controls the output logic state. Reading the PO register shows the current state of the output buffers, independent of the data direction. The port input (PI) register is a read-only register that always reflects the logic state of the I/Os. MAXQ7670 General-Purpose Digital I/Os The MAXQ7670 provides seven general-purpose digital I/Os (GPIOs). Some of the GPIOs include an additional special function (SF), such as a timer input/output. For example, the state of P0.6/T0 is programmable to depend on timer channel 0 logic. When used as a port, each I/O is configurable for high-impedance, weak pullup to DVDDIO or pulldown to GNDIO. At power-up, DVDDIO MAXQ7670 MASTER SLAVE MSB (15) SHIFT REGISTER SFR DATA BUS READ BUFFER DVDDIO LSB(0) MASTER SLAVE MISO MOSI SHIFT CLK SS SCLK OUT SCLK IN MASTER/SLAVE SELECT SPI INTERRUPT SPI CONTROL UNIT SPI ENABLE MASTER SLAVE SCLK SPI CONTRL REG (SPICN) SPI CONTRL REG (SPICF) SYSCLK /2 MASTER (MAX) /8 SLAVE (MAX) 7 SPI CONTRL REG (SPICK) 0 Figure 10. SPI Functional Diagram ______________________________________________________________________________________ 25 Microcontroller with 10-Bit ADC, PGA, 64KB Flash, and CAN Interface MAXQ7670 The drive capability of the I/O, when configured for output, depends on the value in the PS0 (pad drive strength) register and can be set for either 1mA or 2mA. When an I/O is configured as an input, writing to the PO register enables/disables the pullup/pulldown resistor. The value in the PRO (pad resistive pull direction) register sets the enabled resistor at the I/O as either a pullup to DVDDIO or pulldown to GNDIO. Refer to the MAXQ7670 User's Guide for more detailed information. MAXQ20 Core Architecture The MAXQ7670's core is a member of the low-cost, high-performance, CMOS, fully static, 16-bit MAXQ20 core Cs. The MAXQ7670 is structured on a highly advanced, accumulator-based, 16-bit RISC architecture. Fetch and execution operations complete in one cycle without pipelining because the instruction contains both the op code and data. The result is a streamlined 1 million instructions-per-second-per-megahertz (MIPS/MHz) C. The highly efficient core is supported by a 16-level hardware stack, enabling fast subroutine calling and task switching. The internal data pointers manipulate data quickly and efficiently. Multiple data pointers allow more than one function to access data memory without having to save and restore data pointers each time. The data pointers can automatically increment or decrement following an operation, eliminating the need for software intervention and increasing application speed. Port Characteristics The MAXQ7670 includes a bidirectional 7-bit I/O port (P0) whose features include: * Schmitt trigger input circuitry with software-selectable high-impedance or weak pullup to DVDDIO or pulldown to GNDIO * Software-selectable push-pull CMOS output drivers capable of sinking and sourcing 0.5mA * Falling or rising edge interrupt capability * P0.4, P0.6, and P0.7 I/Os contain an additional special function, such as a logic input/output for a timer channel * Selectable pad drive strength and resistive pull direction Refer to the MAXQ7670 User's Guide for more details. Figure 11 illustrates the functional blocks of an I/O. Instruction Set The instruction set is composed of fixed-length, 16-bit instructions that operate on registers and memory locations. The highly orthogonal instruction set allows arithmetic and logical operations to use any register along with the accumulator. Special-function registers (also called peripheral registers) control the peripherals and are subdivided into register modules. The modular family architecture allows new devices and modules to reuse code developed for existing products. The architecture is transport-triggered. This means that writes or reads from certain register locations can also cause side effects to occur. These side effects form the basis for the higher-level op codes defined by the assembler, such as ADDC, OR, JUMP, etc. VDVDDIO P MAXQ7670 Memory Organization PI0._ PR0._ PD0._ PO0._ PS0._ PO0._ PD0._ PULLUP/ PULLDOWN LOGIC N P0._ Figure 11. Digital I/O Circuitry 26 The MAXQ7670 incorporates the following memory areas (see Figure 12): * 8KB (4K x 16) utility ROM * 64KB (32K x 16) of flash memory for program storage * 2048 bytes (1024 x 16) of SRAM for storage of temporary variables * 16-level stack memory for storage of program return addresses and general-purpose use A 16-bit-wide x 16 deep internal hardware stack provides storage for program return addresses and general-purpose use. The MAXQ7670 core implicitly uses the stack when executing an interrupt service routine (ISR) and also when running CALL, RET, and RETI instructions. The stack can also be explicitly used by the ______________________________________________________________________________________ Microcontroller with 10-Bit ADC, PGA, 64KB Flash, and CAN Interface application code to store data when context switching (e.g., during a call or an interrupt). Storing and retrieving data is executed through the PUSH, POP, and POPI instructions. The incorporation of flash memory allows device reprogramming, eliminating the expense of discarding onetime programmable devices during development and field upgrades (see Figure 13 for the flash memory sector maps). A 16-word key protects the flash memory from access by unauthorized individuals. Without supplying the 16word key, the password lock (PWL) bit in the SC register remains set, and the utility ROM is inaccessible. Supplying the 16-word key makes the utility ROM transparent. The password-unlock command is issued through the TAP interface. The 16-word password is compared to the password in the program space to determine its validity. Enabling a pseudo-Von Neumann memory map places the utility ROM, code, and data memory into a single contiguous memory map. Use this mapping scheme for applications that require dynamic program modification or unique memory configurations. MAXQ7670 PAGE 127 7FFFh PAGE 126 PAGE 125 32K x 16 PROGRAM FLASH PAGE 2 0000h PAGE 1 PAGE 0 1 PAGE = 256 WORDS Figure 13. Flash Memory Sector Maps PROGRAM SPACE FFFFh A400h A3FFh 1024 x 16 DATA RAM A000h 8FFFh 4K x 16 UTILITY ROM 8000h 7FFFh DATA SPACE (WORD MODE) FFFFh DATA SPACE (BYTE MODE) FFFFh 9000h 8FFFh 4K x 16 UTILITY ROM 8000h 7FFFh 8K x 8 UTILITY ROM 9000h 8FFFh 8000h 7FFFh 32K x 16 PROGRAM FLASH EXECUTING FROM 1024 x 16 DATA RAM 0000h 0400h 03FFh 2048 x 8 DATA RAM 0000h 0400h 03FFh 0000h Figure 12. MAXQ7670 Memory Map ______________________________________________________________________________________ 27 Microcontroller with 10-Bit ADC, PGA, 64KB Flash, and CAN Interface MAXQ7670 Stack Memory A 16-bit-wide x 16 deep internal hardware stack provides storage for program return addresses and general-purpose use. The processor uses the stack automatically when executing the CALL, RET, and RETI instructions and when servicing interrupts. The stack stores and retrieves data through the PUSH, POP, and POPI instructions. On reset, the stack pointer, SP, initializes to the top of the stack (0Fh). The CALL, PUSH, and interrupt-vectoring operations increment SP, then store a value at the location pointed to by SP. The RET, RETI, POP, and POPI operations retrieve the value at SP and then decrement SP. jumps to the application code at address 0x0000. If the password has not been set (0x0010 to 0x001F is all 0s or all Fs), the ROM code monitors the CAN port for 5s waiting to receive 0x3E. If this character is not detected within 5s, program execution jumps to the application code at address 0x000. If 0x3E is detected during the five-second window, the CAN port is established as the bootloader communication port and the MAXQ7670 responds with 0x3E, verifying that it is in the loader mode. CAN bootloader communication speed is set to 500kbaud when using a 16MHz crystal and 250kbaud when using an 8MHz crystal. Once communication has been established with the loader, the host has access to all the family 0 commands regardless of the state of the PWL bit. If PWL = 0, all the loader commands are accessible. Family 0 commands all start with a 0 and provide basic functionality, but do not allow access to information in either program memory or data memory. This prevents unauthorized access of proprietary information. A mass erase of the flash sets all flash memory including the password to 0xFFFF. With this condition, it is as if no password has been set and the PWL bit is set to 0, which allows access to all loader commands. For more information on password protection and loader commands, refer to the MAXQ7670 User's Guide. Utility ROM The utility ROM is a 8KB (4K x 16) block of internal ROM memory that defaults to a starting address of 8000h. The utility ROM consists of subroutines accessed from application software. These include: * In-system programming (bootstrap loader) over JTAG and CAN * In-circuit debug routines * Routines for in-application flash programming and fast table lookup Following any reset, execution begins in the utility ROM. The ROM software determines whether the program execution should immediately jump to location 0000h, the start of user-application code, or to one of the above routines. Utility ROM routines are accessible in the application software. For more information on the utility ROM contents, refer to the MAXQ7670 User's Guide. Programming Flash Memory The MAXQ7670 allows the user to program its flash through the JTAG or the CAN port by allowing access to the ROM-based bootloader through these ports. The bootloader is entered in one of three ways: by a JTAG request during the power-up sequence, through a CAN request immediately after power-up when no password has been set, and by jumping to the bootloader from the application code. After a reset, the MAXQ7670 instruction pointer jumps to the beginning of ROM code (0x8000). The ROM code does some initial housekeeping and then looks for a request from the JTAG port. If there is a valid request (i.e., SPE = 1, PSS = 00), the processor establishes communication between the ROM bootloader and the JTAG port. If there is no JTAG request and the password has been set (0x0010 to 0x001F is not all 0s or all Fs), then program execution In-Application Programming The in-application programming feature allows the C to modify its own flash program memory while simultaneously executing its application software. This allows on-the-fly software updates in mission-critical applications that cannot afford downtime. In-application programming also allows the application to develop custom loader software that can operate under the control of the application software. The utility ROM contains user-accessible flash programming functions that erase and program flash memory. These functions are described in detail in the MAXQ7670 User's Guide. Register Set Register sets control the MAXQ7670 functions. These registers provide a working space for memory operations as well as configuring and addressing peripheral registers on the device. Registers are divided into two major types: system registers and peripheral registers. The common register set, also known as the system registers, includes the ALU, accumulator registers, data pointers, interrupt vectors and control, and stack pointer. Tables 2-5 show the MAXQ7670 register set. 28 ______________________________________________________________________________________ Microcontroller with 10-Bit ADC, PGA, 64KB Flash, and CAN Interface Power Management Advanced power-management features minimize power consumption by dynamically matching the processing speed of the device to the required performance level. During periods of reduced activity, lower the system clock speed to reduce power consumption. Use the source-clock-divide feature to reduce the system clock speed to 1/2, 1/4, and 1/8 of the source clock's speed. A lower power state is thus achievable without additional hardware. For extremely power-sensitive applications, two additional low-power modes are available: * PMM: divide-by-256 power-management mode (PMME = 1) * Stop mode (STOP = 1) Enabling PMM reduces the system clock speed to 1/256 of the source clock speed, and significantly reduces power consumption. The optional switchback feature allows enabled interrupt sources including external, CAN, and SPI interrupts to bring the C out of the power-management mode and to run at a faster system clock speed. Power consumption is minimal in stop mode. In this mode, the external oscillator, internal RC oscillator, system clock, and all processing activity stop. Triggering an enabled external interrupt or applying an external reset signal to RESET brings the C out of stop mode. Upon exiting stop mode, the C can either wait for the external crystal to warm up, or execute immediately by using the internal RC oscillator as the crystal warms up. Each interrupt has flag and enable bits. The flag indicates whether an interrupt event has occurred. Enable the C to generate an interrupt by setting the enable bit. Interrupts are organized into modules. Enable the interrupt individually, by module, and globally. The C jumps to an ISR after an enabled interrupt event occurs. Use the interrupt identification register (IIR) to determine whether the interrupt is a system or peripheral interrupt. In the ISR, clear the interrupt flag to eliminate repeated interrupts from the same event. After clearing the interrupt, allow a delay before issuing the return from interrupt (RETI) instruction. Asynchronous interrupt flags require a one-instruction delay and synchronous interrupt flags require a two-instruction delay. The MAXQ architecture uses a single interrupt vector (IV) and single ISR design. The IV register holds the address of the ISR. In the application code, assign a unique address to each ISR. Otherwise, the IV automatically jumps to 0000h, the beginning of application code, after an enabled interrupt occurs. MAXQ7670 Reset Sources Reset sources are provided for C control. Although code execution stops in the reset state, the internal RC oscillator continues to oscillate. Internal resets, such as the power-on and watchdog resets, pull RESET low. Power-On Reset (POR) An internal POR circuit enhances system reliability. The POR circuit forces the device to perform a POR whenever a rising voltage on DVDD climbs above the POR threshold. At this point the following events occur: * All registers and circuits enter the default state * The POR flag (WDCN.7) sets to indicate if the source of the reset was a loss of power * The internal 15MHz RC oscillator becomes the clock source * Code execution begins at location 8000h Refer to the MAXQ7670 User's Guide for more information. Interrupts Multiple interrupt sources are available for quick response to internal and external events. Examples of events that can trigger an interrupt are: * Watchdog interrupt * GPIO0-GPIO7 interrupts * SPI mode fault, write collision, receive overrun, and transfer complete interrupts * Timer 0 low compare, low overflow, capture/compare, and overflow interrupts * CAN0 receive and transmit interrupts and a change in CAN0 status register interrupt * ADC data ready interrupt * Voltage brownout interrupts * Crystal oscillator failure interrupt Watchdog Timer Reset The watchdog timer functions are described in the MAXQ7670 User's Guide. Execution resumes at location 8000h following a watchdog timer reset. External System Reset Pulling RESET low externally causes the device to enter the reset state. The external reset functions as described in the MAXQ7670 User's Guide. Execution resumes at location 8000h after RESET is released. ______________________________________________________________________________________ 29 Microcontroller with 10-Bit ADC, PGA, 64KB Flash, and CAN Interface MAXQ7670 Crystal Selection The MAXQ7670 uses an 8MHz or 16MHz Jauch JXG53P2 (or similar specification): Frequency: 8MHz or 16MHz 0.25%. CLOAD: 12pF. CO: < 7pF max. Series resonance resistance: max 50/300 for 16MHz/8MHz, respectively. Note: Series resonance resistance is the resistance observed when the resonator is in the series resonant condition. This is a parameter often stated by quartz crystal vendors and is called R1. When a resonator is used in the parallel resonant mode with an external load capacitance, as is the case with the MAXQ7670 oscillator circuit, the effective resistance is sometimes stated. This effective resistance at the loaded frequency of oscillation is: R1 x (1 + (CO/CLOAD))2 For typical CO and CLOAD values, the effective resistance can be greater than R1 by a factor of two. Development and Technical Support Highly versatile, affordably priced development tools for this C are available from Maxim and third-party suppliers. Tools for the MAXQ7670 include: * Compilers * Evaluation kits * JTAG-to-serial converters for programming and debugging A list of development tool vendors can be found at www.maxim-ic.com/microcontrollers. For technical support, go to www.maxim-ic.com/support. Table 2. System Register Map REGISTER INDEX 0h 1h 2h 3h 4h 5h 6h 7h 8h 9h Ah Bh Ch Dh Eh Fh MODULE NAME (BASE SPECIFIER) AP (8h) AP APC -- -- PSF IC IMR -- SC -- -- IIR -- -- CKCN WDCN A (9h) A[0] A[1] A[2] A[3] A[4] A[5] A[6] A[7] A[8] A[9] A[10] A[11] A[12] A[13] A[14] A[15] -- -- -- -- -- -- -- PFX (Bh) PFX[0] PFX[1] PFX[2] PFX[3] PFX[4] PFX[5] PFX[6] PFX[7] IP (Ch) IP -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- SP (Dh) -- SP IV -- -- -- LC0 LC1 -- -- -- -- -- -- -- -- DPC (Eh) -- -- -- OFFS DPC GR GRL BP GRS GRH GRXL FP -- -- -- -- DP (Fh) -- -- -- DP0 -- -- -- DP1 -- -- -- -- -- -- -- -- 30 ______________________________________________________________________________________ Microcontroller with 10-Bit ADC, PGA, 64KB Flash, and CAN Interface MAXQ7670 Table 3. System Register Bit and Reset Values REGISTER AP APC PSF IC IMR SC IIR CKCN WDCN A[n] (0..15) PFX[n] (0..15) IP SP IV LC[0] LC[1] OFFS DPC GR GRL BP GRS GRH GRXL FP DP[0] DP[1] GR.7 0 0 0 0 GR.7 0 0 0 0 GR.7 0 0 0 0 GR.7 0 0 0 0 GR.7 0 0 0 0 GR.7 0 0 0 0 GR.7 0 0 0 0 -- 0 GR.15 0 -- 0 GR.14 0 -- 0 GR.13 0 -- 0 GR.12 0 -- 0 GR.11 0 -- 0 GR.10 0 -- 0 GR.9 0 0 0 1 -- 0 0 0 0 0 0 0 -- 0 0 0 0 0 0 0 -- 0 0 0 0 0 0 0 -- 0 0 0 0 0 0 0 -- 0 0 0 0 0 0 0 -- 0 0 0 0 0 0 0 -- 0 0 0 0 15 14 13 12 11 10 9 REGISTER BIT 8 7 6 -- -- 0 0 CLR IDS 0 0 Z S 1 0 -- -- 0 0 IMS -- 0 0 TAP -- 1 0 IIS -- 0 0 XT -- s* 0 POR EWDI s* s* A[n] (16 Bits) 0 0 0 PFX[n] (16 Bits) 0 0 0 IP (16 Bits) 0 0 0 -- -- -- 0 0 0 IV (16 Bits) 0 0 0 LC[0] (16 Bits) 0 0 0 LC[1] (16 Bits) 0 0 0 0 0 -- -- 0 0 GR.7 GR.6 0 0 GR.7 GR.6 0 0 BP (16 Bits) 0 0 0 GR.0 GR.15 GR.14 0 0 0 GR.15 GR.14 0 0 GR.7 GR.7 GR.6 0 0 0 FP (16 Bits) 0 0 0 DP[0] (16 Bits) 0 0 0 DP[1] (16 Bits) 0 0 0 5 -- 0 -- 0 -- 0 CGDS 0 IM5 0 CDA1 0 II5 0 RGMD s* WD1 0 0 0 0 -- 0 0 0 0 0 -- 0 GR.5 0 GR.5 0 0 GR.13 0 GR.13 0 GR.5 0 0 0 0 4 -- 0 -- 0 GPF1 0 -- 0 IM4 0 CDA0 0 II4 0 STOP 0 WD0 0 0 0 0 -- 0 0 0 3 0 -- 0 GPF0 0 -- 0 IM3 0 UPA 0 II3 0 SWB 0 WDIF 0 0 0 0 1 0 0 2 1 AP (4 Bits) 0 0 MOD2 MOD1 0 0 OV C 0 0 -- INS 0 0 IM2 IM1 0 0 ROD PWL 0 s* II2 II1 0 0 PMME CD1 0 0 WTRF EWT s* s* 0 0 0 0 0 0 MOD0 0 E 0 IGE 0 IM0 0 -- 0 II0 0 CD0 1 RWT 0 0 0 0 1 0 0 0 0 SDPS0 0 GR.0 0 GR.0 0 0 GR.8 0 GR.8 0 GR.0 0 0 0 0 0 0 SP (4 Bits) 1 1 0 0 0 0 WBS0 1 GR.2 0 GR.2 0 0 GR.10 0 GR.10 0 GR.2 0 0 0 0 0 0 0 0 SDPS1 0 GR.1 0 GR.1 0 0 GR.9 0 GR.9 0 GR.1 0 0 0 0 -- 0 GR.8 0 0 0 OFFS (8 Bits) 0 0 WBS2 WBS1 1 1 GR.4 GR.3 0 0 GR.4 GR.3 0 0 0 GR.12 0 GR.12 0 GR.4 0 0 0 0 0 GR.11 0 GR.11 0 GR.3 0 0 0 0 0 GR.7 0 0 GR.6 0 0 GR.5 0 0 GR.4 0 0 GR.3 0 0 GR.2 0 0 GR.1 0 *Bits indicated by an "s" are only affected by a POR and not by other forms of reset. These bits are set to 0 after a POR. Refer to the MAXQ7670 User's Guide for more information. ______________________________________________________________________________________ 31 Microcontroller with 10-Bit ADC, PGA, 64KB Flash, and CAN Interface MAXQ7670 Table 4. Peripheral Register Map REGISTER INDEX 0h 1h 2h 3h 4h 5h 6h 7h 8h 9h Ah Bh Ch Dh Eh Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh M0 (0h) PO0 -- -- EIFO -- -- -- -- PI0 -- -- EIEO -- -- -- -- PD0 -- -- EIESO -- -- -- -- PS0 -- -- PRO -- -- -- -- M1 (1h) -- -- -- -- -- -- SPIB SPICN SPICF SPICK FCNTL -- -- -- -- -- -- FPCTL -- -- -- -- -- -- -- -- -- -- ID0 -- -- -- M2 (2h) T2CNA0 T2HO T2RHO T2CHO -- -- -- -- T2CNBO T2VO T2RO T2CO -- -- -- -- T2CFG0 -- -- -- -- -- -- -- ICDT0 ICDT1 ICDC ICDF ICDB ICDA ICDD TM M3 (3h) -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- M4 (4h) C0C C0S COIR C0TE C0RE C0R C0DP C0DB C0RMS C0TMA -- -- -- -- -- -- -- C0M1C C0M2C C0M3C C0M4C C0M5C C0M6C C0M7C C0M8C C0M9C C0M10C C0M11C C0M12C C0M13C C0M14C C0M15C M5 (5h) -- APE ACNTL -- -- -- -- -- ADCD -- AIE ASR OSCC -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 32 ______________________________________________________________________________________ Table 5. Peripheral Register Bit Functions and Reset Values REGISTER PO0 EIF0 PI0 EIE0 PD0 EIES0 PS0 PR0 SPIB SPICN SPICF SPICK FCNTL FPCTL ID0 T2CNA0 T2H0 T2RH0 T2CH0 T2CNB0 T2V0 T2R0 T2C0 T2CFG0 ICDT0 ICDT1 ICDC ICDF ICDB MAXQ7670 ______________________________________________________________________________________ ICDA ICDD 15 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 SPIB.15 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 T2V0.15 0 T2R0.15 0 T2C0.15 0 -- 0 ICDT0.15 DB ICDT1.15 DB -- 0 -- 0 -- 0 ICDA.15 0 ICDD.15 0 14 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 SPIB.14 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 T2V0.14 0 T2R0.14 0 T2C0.14 0 -- 0 ICDT0.14 DB ICDT1.14 DB -- 0 -- 0 -- 0 ICDA.14 0 ICDD.14 0 13 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 SPIB.13 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 T2V0.13 0 T2R0.13 0 T2C0.13 0 -- 0 ICDT0.13 DB ICDT1.13 DB -- 0 -- 0 -- 0 ICDA.13 0 ICDD.13 0 12 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 SPIB.12 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 T2V0.12 0 T2R0.12 0 T2C0.12 0 -- 0 ICDT0.12 DB ICDT1.12 DB -- 0 -- 0 -- 0 ICDA.12 0 ICDD.12 0 11 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 SPIB.11 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 T2V0.11 0 T2R0.11 0 T2C0.11 0 -- 0 ICDT0.11 DB ICDT1.11 DB -- 0 -- 0 -- 0 ICDA.11 0 ICDD.11 0 10 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 SPIB.10 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 T2V0.10 0 T2R0.10 0 T2C0.10 0 -- 0 ICDT0.10 DB ICDT1.10 DB -- 0 -- 0 -- 0 ICDA.10 0 ICDD.10 0 9 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 SPIB.9 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 T2V0.9 0 T2R0.9 0 T2C0.9 0 -- 0 ICDT0.9 DB ICDT1.9 DB -- 0 -- 0 -- 0 ICDA.9 0 ICDD.9 0 REGISTER BIT 8 7 -- PO0.7 0 1 -- IE7 0 0 -- PI0.7 0 ST -- EX7 0 0 -- PD0.7 0 0 -- IT7 0 0 -- PS7 0 0 -- PR7 0 0 SPIB.8 SPIB.7 0 0 -- STBY 0 0 -- ESPII 0 0 -- SPICK7 0 0 -- FBUSY 0 1 -- -- 0 0 -- ID0.7 0 0 -- ET2 0 0 -- T2H0.7 0 0 -- T2RH0.7 0 0 -- T2CH0.7 0 0 -- ET2L 0 0 T2V0.8 T2V0.7 0 0 T2R0.8 T2R0.7 0 0 T2C0.8 T2C0.7 0 0 -- T2C1 0 0 ICDT0.8 ICDT0.7 DB DB ICDT1.8 ICDT1.7 DB DB -- DME 0 DW -- -- 0 0 -- ICDB.7 0 0 ICDA.8 ICDA.7 0 0 ICDD.8 ICDD.7 0 0 6 PO0.6 1 IE6 0 PI0.6 ST EX6 0 PD0.6 0 IT6 0 PS6 0 PR6 0 SPIB.6 0 SPIC 0 -- 0 SPICK6 0 -- 0 -- 0 ID0.6 0 T2OE0 0 T2H0.6 0 T2RH0.6 0 T2CH0.6 0 T2OE1 0 T2V0.6 0 T2R0.6 0 T2C0.6 0 T2DIV2 0 ICDT0.6 DB ICDT1.6 DB -- 0 -- 0 ICDB.6 0 ICDA.6 0 ICDD.6 0 5 PO0.5 1 IE5 0 PI0.5 ST EX5 0 PD0.5 0 IT5 0 PS5 0 PR5 0 SPIB.5 0 ROVR 0 -- 0 SPICK5 0 -- 0 -- 0 ID0.5 0 T2POL0 0 T2H0.5 0 T2RH0.5 0 T2CH0.5 0 T2POL1 0 T2V0.5 0 T2R0.5 0 T2C0.5 0 T2DIV1 0 ICDT0.5 DB ICDT1.5 DB REGE DW -- 0 ICDB.5 0 ICDA.5 0 ICDD.5 0 4 PO0.4 1 IE4 0 PI0.4 ST EX4 0 PD0.4 0 IT4 0 PS4 0 PR4 0 SPIB.4 0 WCOL 0 -- 0 SPICK4 0 -- 0 -- 0 ID0.4 0 TR2L 0 T2H0.4 0 T2RH0.4 0 T2CH0.4 0 -- 0 T2V0.4 0 T2R0.4 0 T2C0.4 0 T2DIV0 0 ICDT0.4 DB ICDT1.4 DB -- 0 -- 0 ICDB.4 0 ICDA.4 0 ICDD.4 0 3 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 SPIB.3 0 MODF 0 -- 0 SPICK3 0 -- 0 -- 0 ID0.3 0 TR2 0 T2H0.3 0 T2RH0.3 0 T2CH0.3 0 TF2 0 T2V0.3 0 T2R0.3 0 T2C0.3 0 T2MD 0 ICDT0.3 DB ICDT1.3 DB CMD3 DW PSS1 0 ICDB.3 0 ICDA.3 0 ICDD.3 0 2 PO0.2 1 IE2 0 PI0.2 ST EX2 0 PD0.2 0 IT2 0 PS2 0 PR2 0 SPIB.2 0 MODFE 0 CHR 0 SPICK2 0 FC2 0 -- 0 ID0.2 0 CPRL2 0 T2H0.2 0 T2RH0.2 0 T2CH0.2 0 TF2L 0 T2V0.2 0 T2R0.2 0 T2C0.2 0 CCF1 0 ICDT0.2 DB ICDT1.2 DB CMD2 DW PSS0 0 ICDB.2 0 ICDA.2 0 ICDD.2 0 1 PO0.1 1 IE1 0 PI0.1 ST EX1 0 PDO.1 0 IT1 0 PS1 0 PR1 0 SPIB.1 0 MSTM 0 CKPHA 0 SPICK1 0 FC1 0 -- 0 ID0.1 0 SS2 0 T2H0.1 0 T2RH0.1 0 T2CH0.1 0 TCC2 0 T2V0.1 0 T2R0.1 0 T2C0.1 0 CCF0 0 ICDT0.1 DB ICDT1.1 DB CMD1 DW SPE 0 ICDB.1 0 ICDA.1 0 ICDD.1 0 0 PO0.0 1 IE0 0 PI0.0 ST EX0 0 PD0.0 0 IT0 0 PS0 0 PR0 0 SPIB.0 0 SPIEN 0 CKPOL 0 SPICK0 0 FC0 0 DPMG 0 ID0.0 0 G2EN 0 T2H0.0 0 T2RH0.0 0 T2CH0.0 0 TC2L 0 T2V0.0 0 T2R0.0 0 T2C0.0 0 C/T2 0 ICDT0.0 DB ICDT1.0 DB CMD0 DW TXC 0 ICDB.0 0 ICDA.0 0 ICDD.0 0 Microcontroller with 10-Bit ADC, PGA, 64KB Flash, and CAN Interface 33 MAXQ7670 Microcontroller with 10-Bit ADC, PGA, 64KB Flash, and CAN Interface 34 13 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 C0DP.13 0 C0DB.13 0 C0RMS.14 0 C0TMA.14 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 12 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 C0DP.12 0 C0DB.12 0 C0RMS.13 0 C0TMA.13 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 11 CRTMS 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 C0DP.11 0 C0DB.11 0 C0RMS.12 0 C0TMA.12 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 10 CRTM 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 C0DP.10 0 C0DB.10 0 C0RMS.11 0 C0TMA.11 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 9 TESTCAN 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 C0DP.9 0 C0DB.9 0 C0RMS.10 0 C0TMA.10 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 REGISTER BIT 8 7 -- DCW 0 0 -- ERIE 0 0 -- BSS 0 0 -- INTIN7 0 0 -- C0TE.7 0 0 -- C0RE.7 0 0 -- CAN0BA 0 0 C0DP.8 C0DP.7 0 0 C0DB.8 C0DB.7 0 0 C0RMS.9 C0RMS.8 0 0 C0TMA.9 C0TMA.8 0 0 -- MSRDY 0 0 -- MSRDY 0 0 -- MSRDY 0 0 -- MSRDY 0 0 -- MSRDY 0 0 -- MSRDY 0 0 -- MSRDY 0 0 -- MSRDY 0 0 -- MSRDY 0 0 -- MSRDY 0 0 -- MSRDY 0 0 -- MSRDY 0 0 6 FTEST 0 STIE 0 EC96/128 0 INTIN6 0 C0TE.6 0 C0RE.6 0 INCDEC 0 C0DP.6 0 C0DB.6 0 C0RMS.7 0 C0TMA.7 0 ETI 0 ETI 0 ETI 0 ETI 0 ETI 0 ETI 0 ETI 0 ETI 0 ETI 0 ETI 0 ETI 0 ETI 0 5 DOFF 0 PDE 0 WKS 0 INTIN5 0 C0TE.5 0 C0RE.5 0 AID 0 C0DP.5 0 C0DB.5 0 C0RMS.6 0 C0TMA.6 0 ERI 0 ERI 0 ERI 0 ERI 0 ERI 0 ERI 0 ERI 0 ERI 0 ERI 0 ERI 0 ERI 0 ERI 0 4 -- 0 SIESTA 0 RXS 0 INTIN4 0 C0TE.4 0 C0RE.4 0 C0BPR7 0 C0DP.4 0 C0DB.4 0 C0RMS.5 0 C0TMA.5 0 INTRQ 0 INTRQ 0 INTRQ 0 INTRQ 0 INTRQ 0 INTRQ 0 INTRQ 0 INTRQ 0 INTRQ 0 INTRQ 0 INTRQ 0 INTRQ 0 3 SRT 0 CRST 1 TXS 0 INTIN3 0 C0TE.3 0 C0RE.3 0 C0BPR6 0 C0DP.3 0 C0DB.3 0 C0RMS.4 0 C0TMA.4 0 EXTRQ 0 EXTRQ 0 EXTRQ 0 EXTRQ 0 EXTRQ 0 EXTRQ 0 EXTRQ 0 EXTRQ 0 EXTRQ 0 EXTRQ 0 EXTRQ 0 EXTRQ 0 2 -- 0 AUTOB 0 ER2 0 INTIN2 0 C0TE.2 0 C0RE.2 0 -- 0 C0DP.2 0 C0DB.2 0 C0RMS.3 0 C0TMA.3 0 MTRQ 0 MTRQ 0 MTRQ 0 MTRQ 0 MTRQ 0 MTRQ 0 MTRQ 0 MTRQ 0 MTRQ 0 MTRQ 0 MTRQ 0 MTRQ 0 1 SCANMODE 0 ERCS 0 ER1 0 INTIN1 0 C0TE.1 0 C0RE.1 0 C0BIE 0 C0DP.1 0 C0DB.1 0 C0RMS.2 0 C0TMA.2 0 ROW/TIH 0 ROW/TIH 0 ROW/TIH 0 ROW/TIH 0 ROW/TIH 0 ROW/TIH 0 ROW/TIH 0 ROW/TIH 0 ROW/TIH 0 ROW/TIH 0 ROW/TIH 0 ROW/TIH 0 0 TME 0 SWINT 1 ER0 0 INTIN0 0 C0TE.0 0 C0RE.0 0 C0IE 0 C0DP.0 0 C0DB.0 0 C0RMS.1 0 C0TMA.1 0 DTUP 0 DTUP 0 DTUP 0 DTUP 0 DTUP 0 DTUP 0 DTUP 0 DTUP 0 DTUP 0 DTUP 0 DTUP 0 DTUP 0 Table 5. Peripheral Register Bit Functions and Reset Values (continued) REGISTER TM C0C C0S C0IR C0TE C0RE COR C0DP C0DB C0RMS C0TMA C0M1C C0M2C C0M3C C0M4C C0M5C C0M6C C0M7C C0M8C C0M9C C0M10C C0M11C ______________________________________________________________________________________ C0M12C 15 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 C0DP.15 0 C0DB.15 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 14 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 C0DP.14 0 C0DB.14 0 C0RMS.15 0 C0TMA.15 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 Table 5. Peripheral Register Bit Functions and Reset Values (continued) REGISTER C0M13C C0M14C C0M15C APE ACNT ADCD AIE ASR OSCC 15 -- 0 -- 0 -- 0 -- 0 -- -- -- 0 -- 0 VIOLVL 0 -- 0 14 -- 0 -- 0 -- 0 -- 0 ADCMX3 0 -- 0 -- 0 DVLVL 0 -- 0 13 -- 0 -- 0 -- 0 LRAPD 1 ADCMX2 0 -- 0 -- 0 AVLVL 0 -- 0 12 -- 0 -- 0 -- 0 VIBE 0 ADCMX1 0 -- 0 -- 0 -- 0 -- 0 11 -- 0 -- 0 -- 0 VDBE 0 ADCMX0 0 -- 0 -- 0 XHFRY 0 -- 0 10 -- 0 -- 0 -- 0 VDPE 1 -- 0 -- 0 -- 0 -- 0 -- 0 9 -- 0 -- 0 -- 0 VABE 0 ADCBIP 0 ADCD.9 0 -- 0 -- 0 -- 0 REGISTER BIT 8 7 -- MSRDY 0 0 -- MSRDY 0 0 -- MSRDY 0 0 -- -- 0 0 -- -- 0 0 ADCD.8 ADCD.7 0 0 -- -- 0 0 -- -- 0 0 -- -- 0 0 6 ETI 0 ETI 0 ETI 0 -- 0 ADCDUL 0 ADCD.6 0 HFFIE 0 HFFINT 0 ADCCD1 0 5 ERI 0 ERI 0 ERI 0 PGG0 0 ADCRSEF 0 ADCD.5 0 VIOBIE 0 VIOBI 0 ADCCD0 0 4 INTRQ 0 INTRQ 0 INTRQ 0 -- 0 ADCASD 0 ADCD.4 0 DVBIE 0 DVBI 0 -- 0 3 EXTRQ 0 EXTRQ 0 EXTRQ 0 -- 0 ADCBY 0 ADCD.3 0 AVBIE 0 AVBI 0 -- 0 2 MTRQ 0 MTRQ 0 MTRQ 0 BIASE 0 ADCS2 0 ADCD.2 0 -- 0 -- 0 XTE 0 1 ROW/TIH 0 ROW/TIH 0 ROW/TIH 0 -- 0 ADCS1 0 ADCD.1 0 ADCIE 0 ADCRY 0 RCE 0 0 DTUP 0 DTUP 0 DTUP 0 ADCE 0 ADCS0 0 ADCD.0 0 -- 0 -- 0 -- 0 Bits indicated by "--" are unused. Bits indicated by "DB" have read/write access only in background or debug mode. These bits are cleared after a POR. Bits indicated by "DW" are only written to in debug mode. These bits are cleared after a POR. MAXQ7670 ______________________________________________________________________________________ The OSCC register is cleared to 0002h after a POR and is not affected by other forms of reset. Microcontroller with 10-Bit ADC, PGA, 64KB Flash, and CAN Interface 35 Microcontroller with 10-Bit ADC, PGA, 64KB Flash, and CAN Interface MAXQ7670 Typical Application Circuit DUAL-BRIDGE SENSOR VBRIDGEA OUTA+ -2nF -2nF AIN0 AIN2 AIN4 OUTAR+ dr dr Rdr RR+ dr MUX AIN6 AIN1 AIN3 MUX PGA x16 10-BIT ADC GNDA VBRIDGEB OUTB+ -2nF -2nF dr RR+ dr AIN5 AIN7 OUTBGNDB DUAL-BRIDGE SENSOR VBRIDGEA OUTA+ dr RR+ dr R+ dr dr Rdr R- MAXQ7670 P0.7/T0B P0.6/T0 P0.5 P0.4/ADCCNV -2nF -2nF GPIO 16-BIT TIMER SPI P0.2 P0.1 P0.0 DIGITAL I/O OUTAGNDA VBRIDGEB OUTB+ R+ dr SCLK MISO MOSI SS SPI JTAG -2nF -2nF CAN 2.0B MAXQ20 CORE 16-BIT RISC MICRO 64KB PROGRAM/DATA FLASH 2KB DATA RAM 0.47F dr R- R+ dr OUTBR+ dr dr R- TCK TDI TMS TDO CAN CANTXD CANRXD VDD JTAG S REF TXD MAX13053ASA/AUT RXD VCC 0.1F DVDD +2.5V 0.47F GND CANL 4.7nF 60 TO CAN BUS CANH 60 TO CAN BUS GNDB +3.3V AVDD REFADC +12V 10F IN EN HOLD MAX5024LASA GND OUT SET RESET VDD (+5V) 15F 0.1F 0.1F DVDDIO EXTERNAL RESET IS OPTIONAL RESET XIN 16MHz XOUT I.C. REGEN2 AGND GNDIO DGND 36 ______________________________________________________________________________________ Microcontroller with 10-Bit ADC, PGA, 64KB Flash, and CAN Interface Pin Configuration P0.4/ADCCNV Chip Information PROCESS: CMOS MAXQ7670 TOP VIEW DVDDIO GNDIO RESET DGND DVDD AVDD XOUT P0.5 XIN 40 39 38 37 36 35 34 33 32 31 AIN7 1 AIN6 2 AIN5 3 AIN4 4 REFADC 5 AGND 6 AIN3 7 AIN2 8 AIN1 9 AIN0 10 11 12 13 14 I.C. P0.0 P0.1 P0.2 15 16 17 18 19 20 CANRXD CANTXD SS P0.6/TO P0.7/TOB GNDIO Package Information 30 TCK 29 TDI 28 TMS 27 TDO 26 REGEN2 + *EP For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. PACKAGE TYPE 40 TQFN-EP PACKAGE CODE T4055+1 DOCUMENT NO. 21-0140 MAXQ7670 25 MISO 24 MOSI 23 SCLK 22 GNDIO 21 DVDDIO ______________________________________________________________________________________ 37 Microcontroller with 10-Bit ADC, PGA, 64KB Flash, and CAN Interface MAXQ7670 Revision History REVISION NUMBER 0 1 REVISION DATE 11/08 7/09 Initial release Updated Ordering Information to indicate automotive qualified part DESCRIPTION PAGES CHANGED -- 1 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 38 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2009 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc. |
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